From patchwork Sat Jun 1 18:53:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 54029 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A577C1B9D9; Sat, 1 Jun 2019 20:56:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 1436E4F91 for ; Sat, 1 Jun 2019 20:55:43 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IsiFV029446 for ; Sat, 1 Jun 2019 11:55:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=zjjqvz9tkzweROAEtVSKa4hwdRDpEalE94nHH5taNXg=; b=wxgObNhQEutipF9HYvwdMBqCgicLFNF+72XHPzsqs8FE6AT8HOhKjq4lfE1wNVdf9HEi q6s4zjt8E/b4hXqeyjqOPVMH+z3QHOJy0C3mxDKSLc34OLp1WH5fS7IK6otpUNTtb0A4 xXh5xvYh9bEoJGRaWXVQhvu9d2gSnNHQBSADraaC6cuHtxrsCl9qmU66iljd6dVdWr+/ biBFwYIGbDIPHXSBY6unN4qUXcldw+4wNTb10MjzrpBiA3mUSo1Ohn2ip4cYHqNg6HQk eWDBGEoy/i4pKdFFW9S95PVNt0NtZ+OpPUENQdghNp6fm+s+s3x8PozQomRxx83nnqsm Ug== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk12ds-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:55:43 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:55:42 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:55:42 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id F0E833F7040; Sat, 1 Jun 2019 11:55:40 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:28 +0530 Message-ID: <20190601185355.370-19-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 18/44] event/octeontx2: add SSO dual GWS HW device operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add SSO dual workslot mode GWS HW device operations. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- drivers/event/octeontx2/Makefile | 1 + drivers/event/octeontx2/meson.build | 1 + drivers/event/octeontx2/otx2_worker_dual.c | 6 ++ drivers/event/octeontx2/otx2_worker_dual.h | 76 ++++++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 drivers/event/octeontx2/otx2_worker_dual.c create mode 100644 drivers/event/octeontx2/otx2_worker_dual.h diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile index a3de5ca23..dfecda599 100644 --- a/drivers/event/octeontx2/Makefile +++ b/drivers/event/octeontx2/Makefile @@ -30,6 +30,7 @@ LIBABIVER := 1 # all source are stored in SRCS-y # +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_worker_dual.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_worker.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_irq.c diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build index 1d2080b6d..c2a5f3e3d 100644 --- a/drivers/event/octeontx2/meson.build +++ b/drivers/event/octeontx2/meson.build @@ -3,6 +3,7 @@ # sources = files('otx2_worker.c', + 'otx2_worker_dual.c', 'otx2_evdev.c', 'otx2_evdev_irq.c', ) diff --git a/drivers/event/octeontx2/otx2_worker_dual.c b/drivers/event/octeontx2/otx2_worker_dual.c new file mode 100644 index 000000000..f762436aa --- /dev/null +++ b/drivers/event/octeontx2/otx2_worker_dual.c @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include "otx2_worker_dual.h" +#include "otx2_worker.h" diff --git a/drivers/event/octeontx2/otx2_worker_dual.h b/drivers/event/octeontx2/otx2_worker_dual.h new file mode 100644 index 000000000..fe8813897 --- /dev/null +++ b/drivers/event/octeontx2/otx2_worker_dual.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef __OTX2_WORKER_DUAL_H__ +#define __OTX2_WORKER_DUAL_H__ + +#include +#include + +#include +#include "otx2_evdev.h" + +/* SSO Operations */ +static __rte_always_inline uint16_t +otx2_ssogws_dual_get_work(struct otx2_ssogws_state *ws, + struct otx2_ssogws_state *ws_pair, + struct rte_event *ev) +{ + const uint64_t set_gw = BIT_ULL(16) | 1; + uint64_t get_work0; + uint64_t get_work1; + +#ifdef RTE_ARCH_ARM64 + asm volatile( + " ldr %[tag], [%[tag_loc]] \n" + " ldr %[wqp], [%[wqp_loc]] \n" + " tbz %[tag], 63, done%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldr %[tag], [%[tag_loc]] \n" + " ldr %[wqp], [%[wqp_loc]] \n" + " tbnz %[tag], 63, rty%= \n" + "done%=: str %[gw], [%[pong]] \n" + " prfm pldl1strm, [%[wqp]] \n" + " dmb ld \n" + : [tag] "=&r" (get_work0), [wqp] "=&r" (get_work1) + : [tag_loc] "r" (ws->tag_op), + [wqp_loc] "r" (ws->wqp_op), + [gw] "r" (set_gw), + [pong] "r" (ws_pair->getwrk_op) + ); +#else + get_work0 = otx2_read64(ws->tag_op); + while ((BIT_ULL(63)) & get_work0) + get_work0 = otx2_read64(ws->tag_op); + get_work1 = otx2_read64(ws->wqp_op); + otx2_write64(set_gw, ws_pair->getwrk_op); + + rte_prefetch_non_temporal((const void *)get_work1); +#endif + + ws->cur_tt = (get_work0 >> 32) & 0x3; + ws->cur_grp = (get_work0 >> 36) & 0x3FF; + get_work0 = (get_work0 & (0x3ull << 32)) << 6 | + (get_work0 & (0x3FFull << 36)) << 4 | + (get_work0 & 0xffffffff); + + ev->event = get_work0; + ev->u64 = get_work1; + + return !!get_work1; +} + +static __rte_always_inline void +otx2_ssogws_dual_add_work(struct otx2_ssogws_dual *ws, const uint64_t event_ptr, + const uint32_t tag, const uint8_t new_tt, + const uint16_t grp) +{ + uint64_t add_work0; + + add_work0 = tag | ((uint64_t)(new_tt) << 32); + otx2_store_pair(add_work0, event_ptr, ws->grps_base[grp]); +} + +#endif