diff mbox

[dpdk-dev,v4,3/3] doc: add Broadcom Stingray SoC support to release notes

Message ID 20180410002011.64439-4-ajit.khaparde@broadcom.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Ajit Khaparde April 10, 2018, 12:20 a.m. UTC 
  From: Scott Branden <scott.branden@broadcom.com>

Update 18.05 release notes to indicate support for Broadcom Stingray
SoC support.

Signed-off-by: Scott Branden <scott.branden@broadcom.com>
---
 doc/guides/rel_notes/release_18_05.rst | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

Comments

Ferruh Yigit April 11, 2018, 7:07 p.m. UTC | #1 
On 4/10/2018 1:20 AM, Ajit Khaparde wrote:
> @@ -158,11 +168,10 @@ The libraries prepended with a plus sign were incremented in this version.
>       librte_bus_vdev.so.1
>       librte_cfgfile.so.2
>       librte_cmdline.so.2
> -   + librte_common_octeontx.so.1
>       librte_cryptodev.so.4
>       librte_distributor.so.1
> -   + librte_eal.so.7
> -   + librte_ethdev.so.9
> +     librte_eal.so.6
> +     librte_ethdev.so.8
>       librte_eventdev.so.3
>       librte_flow_classify.so.1
>       librte_gro.so.1

I guess these changes are unintentional, looks like git artifacts, can you
please send a new version?
diff mbox

Patch

diff --git a/doc/guides/rel_notes/release_18_05.rst b/doc/guides/rel_notes/release_18_05.rst
index 0f3d00972..88dcbca7e 100644
--- a/doc/guides/rel_notes/release_18_05.rst
+++ b/doc/guides/rel_notes/release_18_05.rst
@@ -41,6 +41,16 @@  New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Added support for Broadcom NetXtreme-S (BCM58800) family of controllers (aka Stingray) **
+
+  The BCM58800 devices feature a NetXtreme E-Series advanced network controller, a high-performance
+  ARM CPU block, PCI Express (PCIe) Gen3 interfaces, key accelerators for compute offload and a high-
+  speed memory subsystem including L3 cache and DDR4 interfaces, all interconnected by a coherent
+  Network-on-chip (NOC) fabric.
+
+  The ARM CPU subsystem features eight ARMv8 Cortex-A72 CPUs at 3.0 GHz, arranged in a multi-cluster
+  configuration.
+
 * **Added RSS hash and key update to CXGBE PMD.**
 
   Support to update RSS hash and key has been added to CXGBE PMD.
@@ -158,11 +168,10 @@  The libraries prepended with a plus sign were incremented in this version.
      librte_bus_vdev.so.1
      librte_cfgfile.so.2
      librte_cmdline.so.2
-   + librte_common_octeontx.so.1
      librte_cryptodev.so.4
      librte_distributor.so.1
-   + librte_eal.so.7
-   + librte_ethdev.so.9
+     librte_eal.so.6
+     librte_ethdev.so.8
      librte_eventdev.so.3
      librte_flow_classify.so.1
      librte_gro.so.1