diff --git a/app/test-crypto-perf/cperf_test_latency.c b/app/test-crypto-perf/cperf_test_latency.c
index ca2a4ba69e9d..132cf6ebed04 100644
--- a/app/test-crypto-perf/cperf_test_latency.c
+++ b/app/test-crypto-perf/cperf_test_latency.c
@@ -218,7 +218,7 @@ cperf_latency_test_runner(void *arg)
 						burst_size) != 0) {
 				RTE_LOG(ERR, USER1,
 					"Failed to allocate more crypto operations "
-					"from the the crypto operation pool.\n"
+					"from the crypto operation pool.\n"
 					"Consider increasing the pool size "
 					"with --pool-sz\n");
 				return -1;
diff --git a/app/test-crypto-perf/cperf_test_pmd_cyclecount.c b/app/test-crypto-perf/cperf_test_pmd_cyclecount.c
index 9b41724af3ea..529b73ceed88 100644
--- a/app/test-crypto-perf/cperf_test_pmd_cyclecount.c
+++ b/app/test-crypto-perf/cperf_test_pmd_cyclecount.c
@@ -181,7 +181,7 @@ pmd_cyclecount_bench_ops(struct pmd_cyclecount_state *state, uint32_t cur_op,
 					burst_size) != 0) {
 			RTE_LOG(ERR, USER1,
 					"Failed to allocate more crypto operations "
-					"from the the crypto operation pool.\n"
+					"from the crypto operation pool.\n"
 					"Consider increasing the pool size "
 					"with --pool-sz\n");
 				return -1;
@@ -230,7 +230,7 @@ pmd_cyclecount_build_ops(struct pmd_cyclecount_state *state,
 					burst_size) != 0) {
 			RTE_LOG(ERR, USER1,
 					"Failed to allocate more crypto operations "
-					"from the the crypto operation pool.\n"
+					"from the crypto operation pool.\n"
 					"Consider increasing the pool size "
 					"with --pool-sz\n");
 				return -1;
diff --git a/app/test-crypto-perf/cperf_test_throughput.c b/app/test-crypto-perf/cperf_test_throughput.c
index b84dc6304285..8f874fad4f11 100644
--- a/app/test-crypto-perf/cperf_test_throughput.c
+++ b/app/test-crypto-perf/cperf_test_throughput.c
@@ -182,7 +182,7 @@ cperf_throughput_test_runner(void *test_ctx)
 						ops_needed) != 0) {
 				RTE_LOG(ERR, USER1,
 					"Failed to allocate more crypto operations "
-					"from the the crypto operation pool.\n"
+					"from the crypto operation pool.\n"
 					"Consider increasing the pool size "
 					"with --pool-sz\n");
 				return -1;
diff --git a/app/test-crypto-perf/cperf_test_verify.c b/app/test-crypto-perf/cperf_test_verify.c
index 6945c8b4ce30..46a8e6c4e4c5 100644
--- a/app/test-crypto-perf/cperf_test_verify.c
+++ b/app/test-crypto-perf/cperf_test_verify.c
@@ -307,7 +307,7 @@ cperf_verify_test_runner(void *test_ctx)
 					ops_needed) != 0) {
 			RTE_LOG(ERR, USER1,
 				"Failed to allocate more crypto operations "
-				"from the the crypto operation pool.\n"
+				"from the crypto operation pool.\n"
 				"Consider increasing the pool size "
 				"with --pool-sz\n");
 			return -1;
diff --git a/doc/guides/contributing/patches.rst b/doc/guides/contributing/patches.rst
index 40983c15096d..ca82a4b873e3 100644
--- a/doc/guides/contributing/patches.rst
+++ b/doc/guides/contributing/patches.rst
@@ -130,7 +130,7 @@ Make your planned changes in the cloned ``dpdk`` repo. Here are some guidelines
 * Don't break compilation between commits with forward dependencies in a patchset.
   Each commit should compile on its own to allow for ``git bisect`` and continuous integration testing.
 
-* Add tests to the the ``app/test`` unit test framework where possible.
+* Add tests to the ``app/test`` unit test framework where possible.
 
 * Add documentation, if relevant, in the form of Doxygen comments or a User Guide in RST format.
   See the :ref:`Documentation Guidelines <doc_guidelines>`.
@@ -340,7 +340,7 @@ Where the range is a ``git log`` option.
 Checking Compilation
 --------------------
 
-Compilation of patches and changes should be tested using the the ``test-build.sh`` script in the ``devtools``
+Compilation of patches and changes should be tested using the ``test-build.sh`` script in the ``devtools``
 directory of the DPDK repo::
 
   devtools/test-build.sh x86_64-native-linuxapp-gcc+next+shared
diff --git a/doc/guides/linux_gsg/nic_perf_intel_platform.rst b/doc/guides/linux_gsg/nic_perf_intel_platform.rst
index febd733780df..987cd0a5a19c 100644
--- a/doc/guides/linux_gsg/nic_perf_intel_platform.rst
+++ b/doc/guides/linux_gsg/nic_perf_intel_platform.rst
@@ -160,7 +160,7 @@ Configurations before running DPDK
 
       usertools/cpu_layout.py
 
-   Or run ``lscpu`` to check the the cores on each socket.
+   Or run ``lscpu`` to check the cores on each socket.
 
 3. Check your NIC id and related socket id:
 
diff --git a/doc/guides/rel_notes/release_2_1.rst b/doc/guides/rel_notes/release_2_1.rst
index 103a5ee88d2f..e23f1a1777e6 100644
--- a/doc/guides/rel_notes/release_2_1.rst
+++ b/doc/guides/rel_notes/release_2_1.rst
@@ -531,7 +531,7 @@ Resolved Issues
 
 * **eal/linux: Fix irq handling with igb_uio.**
 
-  Fixed an issue where the the introduction of ``uio_pci_generic`` broke
+  Fixed an issue where the introduction of ``uio_pci_generic`` broke
   interrupt handling with igb_uio.
 
   Fixes: c112df6875a5 ("eal/linux: toggle interrupt for uio_pci_generic")
diff --git a/doc/guides/sample_app_ug/keep_alive.rst b/doc/guides/sample_app_ug/keep_alive.rst
index 9b8be4890a87..38856d2c6e03 100644
--- a/doc/guides/sample_app_ug/keep_alive.rst
+++ b/doc/guides/sample_app_ug/keep_alive.rst
@@ -148,7 +148,7 @@ is configured to run every check_period milliseconds.
         rte_exit(EXIT_FAILURE, "Keepalive setup failure.\n");
 
 The rest of the initialization and run-time path follows
-the same paths as the the L2 forwarding application. The only
+the same paths as the L2 forwarding application. The only
 addition to the main processing loop is the mark alive
 functionality and the example random failures.
 
diff --git a/doc/guides/sample_app_ug/performance_thread.rst b/doc/guides/sample_app_ug/performance_thread.rst
index 57391caffca2..5dad83fdf175 100644
--- a/doc/guides/sample_app_ug/performance_thread.rst
+++ b/doc/guides/sample_app_ug/performance_thread.rst
@@ -310,7 +310,7 @@ interconnected via software rings.
 On initialization an L-thread scheduler is started on every EAL thread. On all
 but the master EAL thread only a a dummy L-thread is initially started.
 The L-thread started on the master EAL thread then spawns other L-threads on
-different L-thread schedulers according the the command line parameters.
+different L-thread schedulers according the command line parameters.
 
 The RX threads poll the network interface queues and post received packets
 to a TX thread via the corresponding software ring.
diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
index df22f2a952ae..59d364eb9d03 100644
--- a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
@@ -227,7 +227,7 @@ int
 rte_cryptodev_scheduler_ordering_get(uint8_t scheduler_id);
 
 /**
- * Get the the attached slaves' count and/or ID
+ * Get the attached slaves' count and/or ID
  *
  * @param scheduler_id
  *   The target scheduler device ID
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index c16edbadb50d..898c3edaeffe 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -909,7 +909,7 @@ struct rx_pkt_cmpl {
 	 * This is the length of the data for the packet stored in the
 	 * buffer(s) identified by the opaque value. This includes the
 	 * packet BD and any associated buffer BDs. This does not
-	 * include the the length of any data places in aggregation BDs.
+	 * include the length of any data places in aggregation BDs.
 	 */
 	uint32_t opaque;
 	/*
@@ -3275,7 +3275,7 @@ struct hwrm_func_cfg_input {
 	uint16_t fid;
 	/*
 	 * Function ID of the function that is being configured. If set
-	 * to 0xFF...	(All Fs), then the the configuration is for the
+	 * to 0xFF...	(All Fs), then the configuration is for the
 	 * requesting function.
 	 */
 	uint8_t unused_0;
diff --git a/drivers/net/e1000/base/e1000_82575.c b/drivers/net/e1000/base/e1000_82575.c
index c6400bde706b..15c7dd84458b 100644
--- a/drivers/net/e1000/base/e1000_82575.c
+++ b/drivers/net/e1000/base/e1000_82575.c
@@ -2414,7 +2414,7 @@ STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
  *  @hw: pointer to the HW structure
  *
- *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
+ *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
  *  the values found in the EEPROM.  This addresses an issue in which these
  *  bits are not restored from EEPROM after reset.
  **/
diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index 6dd046d2f636..92ab6fc6ca86 100644
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -4888,7 +4888,7 @@ STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
  *  @hw: pointer to the HW structure
  *
  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
- *  register, so the the bus width is hard coded.
+ *  register, so the bus width is hard coded.
  **/
 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
 {
diff --git a/drivers/net/fm10k/base/fm10k_mbx.c b/drivers/net/fm10k/base/fm10k_mbx.c
index 16ab98d39101..e766e45cef33 100644
--- a/drivers/net/fm10k/base/fm10k_mbx.c
+++ b/drivers/net/fm10k/base/fm10k_mbx.c
@@ -850,7 +850,7 @@ STATIC s32 fm10k_mbx_read(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx)
  *  @hw: pointer to hardware structure
  *  @mbx: pointer to mailbox
  *
- *  This function copies the message from the the message array to mbmem
+ *  This function copies the message from the message array to mbmem
  **/
 STATIC void fm10k_mbx_write(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx)
 {
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index cd67453d1a69..1610fdc10861 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -353,7 +353,7 @@ struct i40e_vsi {
 	 * needs to add, HW needs to know the layout that VSIs are organized.
 	 * Besides that, VSI isan element and can't switch packets, which needs
 	 * to add new component VEB to perform switching. So, a new VSI needs
-	 * to specify the the uplink VSI (Parent VSI) before created. The
+	 * to specify the uplink VSI (Parent VSI) before created. The
 	 * uplink VSI will check whether it had a VEB to switch packets. If no,
 	 * it will try to create one. Then, uplink VSI will move the new VSI
 	 * into its' sib_vsi_list to manage all the downlink VSI.
diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c
index 9862391b986c..f7401c0609e7 100644
--- a/drivers/net/ixgbe/base/ixgbe_x550.c
+++ b/drivers/net/ixgbe/base/ixgbe_x550.c
@@ -2790,7 +2790,7 @@ STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
  *  @hw: pointer to hardware structure
  *
- *  Configure the the integrated PHY for SFP support.
+ *  Configure the integrated PHY for SFP support.
  **/
 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
 				    ixgbe_link_speed speed,
diff --git a/drivers/net/qede/base/ecore_chain.h b/drivers/net/qede/base/ecore_chain.h
index ba272a911482..d8f69ad65cb1 100644
--- a/drivers/net/qede/base/ecore_chain.h
+++ b/drivers/net/qede/base/ecore_chain.h
@@ -128,7 +128,7 @@ struct ecore_chain {
 	} pbl_sp;
 
 	/* Address of first page of the chain  - the address is required
-	 * for fastpath operation [consume/produce] but only for the the SINGLE
+	 * for fastpath operation [consume/produce] but only for the SINGLE
 	 * flavour which isn't considered fastpath [== SPQ].
 	 */
 	void				*p_virt_addr;
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index da1830ced556..744d20430322 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -3182,7 +3182,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
 	 * resources allocation queries should be atomic. Since several PFs can
 	 * run in parallel - a resource lock is needed.
 	 * If either the resource lock or resource set value commands are not
-	 * supported - skip the the max values setting, release the lock if
+	 * supported - skip the max values setting, release the lock if
 	 * needed, and proceed to the queries. Other failures, including a
 	 * failure to acquire the lock, will cause this function to fail.
 	 * Old drivers that don't acquire the lock can run in parallel, and
diff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h
index be3e91f0096f..225890e289ad 100644
--- a/drivers/net/qede/base/ecore_mcp_api.h
+++ b/drivers/net/qede/base/ecore_mcp_api.h
@@ -552,7 +552,7 @@ struct ecore_mcp_link_capabilities
 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn);
 
 /**
- * @brief Request the MFW to set the the link according to 'link_input'.
+ * @brief Request the MFW to set the link according to 'link_input'.
  *
  * @param p_hwfn
  * @param p_ptt
diff --git a/drivers/net/qede/base/ecore_proto_if.h b/drivers/net/qede/base/ecore_proto_if.h
index 66622323952e..abca7408dea1 100644
--- a/drivers/net/qede/base/ecore_proto_if.h
+++ b/drivers/net/qede/base/ecore_proto_if.h
@@ -33,7 +33,7 @@ struct ecore_eth_pf_params {
 	u32	num_arfs_filters;
 };
 
-/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
+/* Most of the parameters below are described in the FW iSCSI / TCP HSI */
 struct ecore_iscsi_pf_params {
 	u64		glbl_q_params_addr;
 	u64		bdq_pbl_base_addr[2];
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 58d1b0af93aa..83c958c436d6 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1159,7 +1159,7 @@ ef10_get_privilege_mask(
  * For the Huntington family, the current port mode cannot be discovered,
  * so the mapping used is instead the last match in the table to the full
  * set of port modes to which the NIC can be configured. Therefore the
- * ordering of entries in the the mapping table is significant.
+ * ordering of entries in the mapping table is significant.
  */
 static struct {
 	efx_family_t	family;
diff --git a/examples/performance-thread/common/lthread_tls.c b/examples/performance-thread/common/lthread_tls.c
index 2259fad44778..ba758405d32e 100644
--- a/examples/performance-thread/common/lthread_tls.c
+++ b/examples/performance-thread/common/lthread_tls.c
@@ -111,7 +111,7 @@ void _lthread_key_pool_init(void)
 
 /*
  * Create a key
- * this means getting a key from the the pool
+ * this means getting a key from the pool
  */
 int lthread_key_create(unsigned int *key, tls_destructor_func destructor)
 {
diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h
index 7b81705b3fba..6cc9e62d4db6 100644
--- a/lib/librte_eal/common/include/generic/rte_atomic.h
+++ b/lib/librte_eal/common/include/generic/rte_atomic.h
@@ -78,7 +78,7 @@ static inline void rte_rmb(void);
  *
  * Guarantees that the LOAD and STORE operations that precede the
  * rte_smp_mb() call are globally visible across the lcores
- * before the the LOAD and STORE operations that follows it.
+ * before the LOAD and STORE operations that follows it.
  */
 static inline void rte_smp_mb(void);
 
@@ -87,7 +87,7 @@ static inline void rte_smp_mb(void);
  *
  * Guarantees that the STORE operations that precede the
  * rte_smp_wmb() call are globally visible across the lcores
- * before the the STORE operations that follows it.
+ * before the STORE operations that follows it.
  */
 static inline void rte_smp_wmb(void);
 
@@ -96,7 +96,7 @@ static inline void rte_smp_wmb(void);
  *
  * Guarantees that the LOAD operations that precede the
  * rte_smp_rmb() call are globally visible across the lcores
- * before the the LOAD operations that follows it.
+ * before the LOAD operations that follows it.
  */
 static inline void rte_smp_rmb(void);
 
diff --git a/lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_82575.c b/lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_82575.c
index 5da7f91fd1cb..60521a73b500 100644
--- a/lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_82575.c
+++ b/lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_82575.c
@@ -2380,7 +2380,7 @@ static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
  *  @hw: pointer to the HW structure
  *
- *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
+ *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
  *  the values found in the EEPROM.  This addresses an issue in which these
  *  bits are not restored from EEPROM after reset.
  **/
diff --git a/lib/librte_power/rte_power_acpi_cpufreq.c b/lib/librte_power/rte_power_acpi_cpufreq.c
index 6b0cdb2eb4a0..aac715a27ea8 100644
--- a/lib/librte_power/rte_power_acpi_cpufreq.c
+++ b/lib/librte_power/rte_power_acpi_cpufreq.c
@@ -372,7 +372,7 @@ rte_power_acpi_cpufreq_init(unsigned lcore_id)
 
 /**
  * It is to check the governor and then set the original governor back if
- * needed by writing the the sys file.
+ * needed by writing the sys file.
  */
 static int
 power_set_governor_original(struct rte_power_info *pi)
