From patchwork Sat Sep 9 11:20:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 28532 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 22CFA1B1AF; Sat, 9 Sep 2017 13:10:53 +0200 (CEST) Received: from NAM03-DM3-obe.outbound.protection.outlook.com (mail-dm3nam03on0077.outbound.protection.outlook.com [104.47.41.77]) by dpdk.org (Postfix) with ESMTP id 906071B1A1 for ; Sat, 9 Sep 2017 13:10:49 +0200 (CEST) Received: from MWHPR03CA0033.namprd03.prod.outlook.com (2603:10b6:301:3b::22) by DM2PR03MB557.namprd03.prod.outlook.com (2a01:111:e400:241b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.13.10; Sat, 9 Sep 2017 11:10:46 +0000 Received: from BY2FFO11FD048.protection.gbl (2a01:111:f400:7c0c::120) by MWHPR03CA0033.outlook.office365.com (2603:10b6:301:3b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.35.12 via Frontend Transport; Sat, 9 Sep 2017 11:10:46 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD048.mail.protection.outlook.com (10.1.15.176) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1385.11 via Frontend Transport; Sat, 9 Sep 2017 11:10:46 +0000 Received: from Tophie.ap.freescale.net ([10.232.14.39]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id v89BAUh7026326; Sat, 9 Sep 2017 04:10:44 -0700 From: Shreyansh Jain To: CC: , Date: Sat, 9 Sep 2017 16:50:58 +0530 Message-ID: <20170909112132.13936-8-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170909112132.13936-1-shreyansh.jain@nxp.com> References: <20170823141213.25476-1-shreyansh.jain@nxp.com> <20170909112132.13936-1-shreyansh.jain@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131494290466294091; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(336005)(39380400002)(39860400002)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(2351001)(33646002)(105606002)(106466001)(5003940100001)(5660300001)(36756003)(53936002)(575784001)(8656003)(54906002)(85426001)(498600001)(8936002)(48376002)(50466002)(2906002)(86362001)(81156014)(81166006)(50986999)(6666003)(76176999)(50226002)(77096006)(6916009)(2950100002)(1076002)(97736004)(189998001)(104016004)(356003)(305945005)(47776003)(110136004)(4326008)(8676002)(68736007)(2004002)(217873001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM2PR03MB557; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD048; 1:J1b96uTd3t+ZN4QBNAkzXsNBdyzqqvRn6xEAGYXJYMGXVCiKso/9Nxq7LIFVgTePGNtfhf04H5cPLpfLvQsHdr7Co+xitaqrqraBJCWx5hOIJHdVyuUHfpGADumBZztt MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4ae2d566-7114-41ff-494b-08d4f7736bb3 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603199)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:DM2PR03MB557; X-Microsoft-Exchange-Diagnostics: 1; DM2PR03MB557; 3:Wm5b3tQSHk22NaawFyOtXWaIqrJxlAEHuBOcJa9l5366P+oX9IrfetEHPlrEPhIL82OM8QgcG9wUys56Sq+cTtRJ5zelGlH0tqpVg/BZaU77rdmTo593bO9bSd4fsmuAHYEcZdpRuqv+FTWqsGwpyUxweCdbQl1Wh6LPrN6D0FD2wdotGpRNA/86fcsh9vAgehNXs9yiHLlPoJvpFQnIedWXjH1cTZrr99gKViHTK0YtbGzQKxBZArGsBeKEhXmEhG8Df31Ymqaq5H9Bu9waXpvsJarPD1m6yvsDBPG1xDA/O+ICguEoIyzWf6L7O3l7K5CS17uRC6c1HRoNMFaztsRnfaENfYtVeLP4rNfegFY=; 25:VebHdO0XIOaOO1w7zIqI4o8MARaF0pD+d1c1EA+3azg3/Gx1kbZNgI5N1eLxc0yADJyxgX51ILW285kAAsmbDFvMkbHzcoDlVyEH2TTWaJ0rztNU6TbkMxuoBGQkqZ8WbPscCk/yTV8oPSs4e+2jVG5BR67Ac8um34azR9vj6DPyavCqcGZVA+xfSFaqMOTczFgO443atTTDDKWnrjFnHbncohHMvSwNLe+V9f0R0huXv78A33xQt7zsxIdHkZcnJj/fN6dGGbeWinGZD6WaU+KvIqvxpUthyqfkFDZoI0O5Z9n9mIHF5CP399AiuZX8r9seRxD2Sv4kpIi1fppxSQ== X-MS-TrafficTypeDiagnostic: DM2PR03MB557: X-Microsoft-Exchange-Diagnostics: 1; DM2PR03MB557; 31:suEuEkGONEpNTVDXGNEUYklR1rKSrKA9hJAzh5exDqtMnttZgfkQWvQGAajzWKRbT1Zg7Rvq4z9EClo5xsglZNb8CI2tLqpvQHxAphFBWVSFgV76d663Bx2AQmWn4x/3qCtaao4sdTaPB7nm/c8psA/NGmD/4AFbb9a1m9bcTYEpx3Lk2Or+ECoV/7tSkLM/hnJBjd+viWUpVA4p/DIW2zL3jLm1hvqeFNFRP0qL1kc=; 4:MSIuCPXKilcxVbm+mORVoswzpHpVzzLHrbens9fWrREutshCbjLbaIJ+OKcLpLD8wzozkTfD1Oejx0+jjephKh3C6YIRZDa+3LZ0dpfKmQ+JU9Z2mMZoLC7xcQhtlUZ+bTB33xptNh5YgM0EHavdLN3z32DLJXwML38J6kSGRTx9+xR1xD9cB0fCaQKDUAVqRmNAcIZYEHtvbDXEzO25XM/QJmu4YdNjkPaORbUfFD3d2mA+hHWV0Shbjrqq6iyMJ/7NCErWwqy90rrePS85+vnB3rDvBtDIUidPscDr6M2tMhPdHvxaaa5OS81tl4Ehv0iQtmrWOUna38Y02E3Sdr99iaWh8bxQwnNiGDKYbt5MUJ7t2+bo11C07A9Wbiv0ZiAKA885Vq4Fbc9ZZn0+D8uePGNVyQeFesQf7cDYZ+7IDmdnV3igjoPpFMmPH6B/ X-Exchange-Antispam-Report-Test: UriScan:(278428928389397)(35073007944872)(185117386973197)(227817650892897)(275809806118684); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(5005006)(8121501046)(10201501046)(93006095)(93001095)(100000703101)(100105400095)(3002001)(6055026)(6096035)(20161123556025)(201703131430075)(201703131448075)(201703131433075)(201703161259150)(201703151042153)(20161123561025)(20161123565025)(20161123563025)(20161123559100)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DM2PR03MB557; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DM2PR03MB557; X-Forefront-PRVS: 0425A67DEF X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM2PR03MB557; 23:Htx22Z0iHWnm5bUv5oJEtV0vL5wpavkysNnx9fKBlq?= NMruq1MR2JUIH2FubosXhRL+lcFKYjIUzQATI0ta1yn2l7vUR1EMblq2cDvpMcr8UUqRnCzhHo3b/YOnfLfsa+1yUh4WJN/tFHx6O7cbjOLgAJe8ufP1VO72AFL/luDZ5EFnHFFqaprHgNP6irJEHnpuLhpdgmr36reps06RVRVEnWKjDu8WZIfuyHHTyKdrcTLNXTcVvdtdcV4sNnpkDJyWgSVM/rQvDk4+wfdJwj6wblv0Lxn9iFvcOMseCgyGLwov0zcmXTHyBz+PAEwkWUpZeXvMNSL7gr03wi9M8NNg5DW9sAoHOrbNxtQyXPkyYoWZav8Nrc+xeR90Hr4Dl0vKmWMOrbXhpqQ0vIdxv/nj4gNxhlwB94e7AW+rf8hoeOiSSqTcgqzZEys5C06ZAJBlrbxjSGr13VOOYzFIUyoP+PycQ7Ul2qG37UVtRLDMsWhBKjwWRxSYz9VnBhaigSIx/ddfkP387aifmXnPE7wJyuDznAuO+HguLKb0jH2xWbPP8lhVDnMoaNz/HxkxJoWpmVBbdteX9/m+JFktDMk6s3i/4c5lnfDfW8GXyjtq2jEBvPjkWsOmtDwtmUZkjSfo4ccPLETbAaw9QkCUe4761MCzXzJj6X0sNZRQX9vX7BOqEi/FymZSxMuoB3Z+MpLk/2ro7TdcgsVUuwkbBO9cedxWkBHN3S2som/swE4D85pOkDhsQGdRNUx7kbEj9flqaYpQ6eKoUmYvx5kvzcAC+tOAfClPMXknVzBr4c6P41vxwssljPiTUjtOonftBrTG9euda4ORA8SkrNAxf4kRrLKPQSO/mmD9VTFCma1GbgB/crhc+9EjVy/Ln/l2mPfEydk74+jxTk9fkrT5DWHwsemABYjixdYDKAAPMOGKIlWYVu54h8vyuYuM2X2pEA3C0i1E8exLnqFvKXxomTTc4IHkgUzR0yr33ooNI2TuMkNEBTBMQGc9HQbwTM7W4pzSN87S9cRsF3fbvmlzcq4d+5WMg6VmXmUO/loR94+fcvGFiXN3dYCl4mGV7Mz2gGPA1GYdmrZySt5GpcAFG8TWSrnQgn6WLjiP1T7cYJJUCbs/A8QpMexoksZLT2B22No5WQqayxtF8jHtMnJovbUN/BYp1hHIlA4WkW4QHC1CKoAsNinxh2GklAw6bvJ1VE X-Microsoft-Exchange-Diagnostics: 1; DM2PR03MB557; 6:ytJFbArSLUnXa/XdaJZRkJcNBGDO2UyfxO0ZSr3Y3VsfSRJMaDoK3YHX2x1SKIbo3iTomykRqv5SVgqruN4w1lHt5bQEfYcSSMXBqobZ3UuqUOxv7BWloKAAP4fIH6cBOxwm3PGK70MFamAoRGIz+yPlNkqNY0JCc59kt1Eaz5fV61fY+7869PKvdwPv+mFkoiDx1KrGd+5xEKz2KSWwP6IUcMaj0kTpohwemIOShU6pL+ZxC1eC8GHstdHrjyoy/aejc6cbq6HXZdmwFSucvJMEVCsPyfoGZmlQgcntKD03tPlQeLUizR4nI7L9a3I2eE1wY7ky6gKXib0IMaZc4g==; 5:x1eOo+J69vwKOUuveLx6fGb653jKL9Fr34wqwqrXOleiIOaD0mcQStxAj6i3DMM23Pw2Zbk3qmGg0GcVWPvNn+UOAN0xY7uv65YgqhiCY4LfuA0VODjnLL2EwrRQbi4fZ/1XRI5PAbMHEiz3Xw7CqA==; 24:Yoo0Oa5U5fHKxjLm3m4Hjmad5FUlAF6fXI/71ZiTKG5f4lFW8LxNFUm//7h92AzBpFQwbAnkeYo+9vOib9iuYLS8GlNqs6yjrJbBBiBUvhA=; 7:/zCDJWDFbWDccOgJwnCHQN3F3qA1pu41W9cHVR0QGN2QNjnpofgRc7okmi6iMJd+viDQAekGzrZLMgBTvNUuKA9MN4IFmRD06Vn5B5Wu78uIgb0PQepPiQGclfrVxq079033hJfPLy4pdcAT4COuEGwsxorEKf17HqEczCZ4UlMzXB4B7SJFEIr+3j9IcBcqikQDTrsvVHMJSqwPDdocg35xAamY6rD4koKTDcoI/4A= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2017 11:10:46.4266 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR03MB557 Subject: [dpdk-dev] [PATCH v4 07/41] bus/dpaa: enable DPAA IOCTL portal driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Userspace applications interact with DPAA blocks using this IOCTL driver. Signed-off-by: Geoff Thorpe Signed-off-by: Hemant Agrawal Signed-off-by: Shreyansh Jain --- drivers/bus/dpaa/Makefile | 4 +- drivers/bus/dpaa/base/qbman/process.c | 331 ++++++++++++++++++++++++++++++++++ drivers/bus/dpaa/include/fsl_usd.h | 88 +++++++++ drivers/bus/dpaa/include/process.h | 107 +++++++++++ 4 files changed, 529 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/dpaa/base/qbman/process.c create mode 100644 drivers/bus/dpaa/include/fsl_usd.h create mode 100644 drivers/bus/dpaa/include/process.h diff --git a/drivers/bus/dpaa/Makefile b/drivers/bus/dpaa/Makefile index 9f416fe..b0083c9 100644 --- a/drivers/bus/dpaa/Makefile +++ b/drivers/bus/dpaa/Makefile @@ -50,6 +50,7 @@ CFLAGS += -D _GNU_SOURCE CFLAGS += -I$(RTE_BUS_DPAA)/ CFLAGS += -I$(RTE_BUS_DPAA)/include +CFLAGS += -I$(RTE_BUS_DPAA)/base/qbman CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common/include @@ -67,6 +68,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += \ base/fman/fman.c \ base/fman/fman_hw.c \ base/fman/of.c \ - base/fman/netcfg_layer.c + base/fman/netcfg_layer.c \ + base/qbman/process.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/bus/dpaa/base/qbman/process.c b/drivers/bus/dpaa/base/qbman/process.c new file mode 100644 index 0000000..b8ec539 --- /dev/null +++ b/drivers/bus/dpaa/base/qbman/process.c @@ -0,0 +1,331 @@ +/*- + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * BSD LICENSE + * + * Copyright 2011-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * GPL LICENSE SUMMARY + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +#include "process.h" + +#include + +/* As higher-level drivers will be built on top of this (dma_mem, qbman, ...), + * it's preferable that the process driver itself not provide any exported API. + * As such, combined with the fact that none of these operations are + * performance critical, it is justified to use lazy initialisation, so that's + * what the lock is for. + */ +static int fd = -1; +static pthread_mutex_t fd_init_lock = PTHREAD_MUTEX_INITIALIZER; + +static int check_fd(void) +{ + int ret; + + if (fd >= 0) + return 0; + ret = pthread_mutex_lock(&fd_init_lock); + assert(!ret); + /* check again with the lock held */ + if (fd < 0) + fd = open(PROCESS_PATH, O_RDWR); + ret = pthread_mutex_unlock(&fd_init_lock); + assert(!ret); + return (fd >= 0) ? 0 : -ENODEV; +} + +#define DPAA_IOCTL_MAGIC 'u' +struct dpaa_ioctl_id_alloc { + uint32_t base; /* Return value, the start of the allocated range */ + enum dpaa_id_type id_type; /* what kind of resource(s) to allocate */ + uint32_t num; /* how many IDs to allocate (and return value) */ + uint32_t align; /* must be a power of 2, 0 is treated like 1 */ + int partial; /* whether to allow less than 'num' */ +}; + +struct dpaa_ioctl_id_release { + /* Input; */ + enum dpaa_id_type id_type; + uint32_t base; + uint32_t num; +}; + +struct dpaa_ioctl_id_reserve { + enum dpaa_id_type id_type; + uint32_t base; + uint32_t num; +}; + +#define DPAA_IOCTL_ID_ALLOC \ + _IOWR(DPAA_IOCTL_MAGIC, 0x01, struct dpaa_ioctl_id_alloc) +#define DPAA_IOCTL_ID_RELEASE \ + _IOW(DPAA_IOCTL_MAGIC, 0x02, struct dpaa_ioctl_id_release) +#define DPAA_IOCTL_ID_RESERVE \ + _IOW(DPAA_IOCTL_MAGIC, 0x0A, struct dpaa_ioctl_id_reserve) + +int process_alloc(enum dpaa_id_type id_type, uint32_t *base, uint32_t num, + uint32_t align, int partial) +{ + struct dpaa_ioctl_id_alloc id = { + .id_type = id_type, + .num = num, + .align = align, + .partial = partial + }; + int ret = check_fd(); + + if (ret) + return ret; + ret = ioctl(fd, DPAA_IOCTL_ID_ALLOC, &id); + if (ret) + return ret; + for (ret = 0; ret < (int)id.num; ret++) + base[ret] = id.base + ret; + return id.num; +} + +void process_release(enum dpaa_id_type id_type, uint32_t base, uint32_t num) +{ + struct dpaa_ioctl_id_release id = { + .id_type = id_type, + .base = base, + .num = num + }; + int ret = check_fd(); + + if (ret) { + fprintf(stderr, "Process FD failure\n"); + return; + } + ret = ioctl(fd, DPAA_IOCTL_ID_RELEASE, &id); + if (ret) + fprintf(stderr, "Process FD ioctl failure type %d base 0x%x num %d\n", + id_type, base, num); +} + +int process_reserve(enum dpaa_id_type id_type, uint32_t base, uint32_t num) +{ + struct dpaa_ioctl_id_reserve id = { + .id_type = id_type, + .base = base, + .num = num + }; + int ret = check_fd(); + + if (ret) + return ret; + return ioctl(fd, DPAA_IOCTL_ID_RESERVE, &id); +} + +/***************************************/ +/* Mapping and using QMan/BMan portals */ +/***************************************/ + +#define DPAA_IOCTL_PORTAL_MAP \ + _IOWR(DPAA_IOCTL_MAGIC, 0x07, struct dpaa_ioctl_portal_map) +#define DPAA_IOCTL_PORTAL_UNMAP \ + _IOW(DPAA_IOCTL_MAGIC, 0x08, struct dpaa_portal_map) + +int process_portal_map(struct dpaa_ioctl_portal_map *params) +{ + int ret = check_fd(); + + if (ret) + return ret; + + ret = ioctl(fd, DPAA_IOCTL_PORTAL_MAP, params); + if (ret) { + perror("ioctl(DPAA_IOCTL_PORTAL_MAP)"); + return ret; + } + return 0; +} + +int process_portal_unmap(struct dpaa_portal_map *map) +{ + int ret = check_fd(); + + if (ret) + return ret; + + ret = ioctl(fd, DPAA_IOCTL_PORTAL_UNMAP, map); + if (ret) { + perror("ioctl(DPAA_IOCTL_PORTAL_UNMAP)"); + return ret; + } + return 0; +} + +#define DPAA_IOCTL_PORTAL_IRQ_MAP \ + _IOW(DPAA_IOCTL_MAGIC, 0x09, struct dpaa_ioctl_irq_map) + +int process_portal_irq_map(int ifd, struct dpaa_ioctl_irq_map *map) +{ + map->fd = fd; + return ioctl(ifd, DPAA_IOCTL_PORTAL_IRQ_MAP, map); +} + +int process_portal_irq_unmap(int ifd) +{ + return close(ifd); +} + +struct dpaa_ioctl_raw_portal { + /* inputs */ + enum dpaa_portal_type type; /* Type of portal to allocate */ + + uint8_t enable_stash; /* set to non zero to turn on stashing */ + /* Stashing attributes for the portal */ + uint32_t cpu; + uint32_t cache; + uint32_t window; + /* Specifies the stash request queue this portal should use */ + uint8_t sdest; + + /* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX + * for don't care. The portal index will be populated by the + * driver when the ioctl() successfully completes. + */ + uint32_t index; + + /* outputs */ + uint64_t cinh; + uint64_t cena; +}; + +#define DPAA_IOCTL_ALLOC_RAW_PORTAL \ + _IOWR(DPAA_IOCTL_MAGIC, 0x0C, struct dpaa_ioctl_raw_portal) + +#define DPAA_IOCTL_FREE_RAW_PORTAL \ + _IOR(DPAA_IOCTL_MAGIC, 0x0D, struct dpaa_ioctl_raw_portal) + +static int process_portal_allocate(struct dpaa_ioctl_raw_portal *portal) +{ + int ret = check_fd(); + + if (ret) + return ret; + + ret = ioctl(fd, DPAA_IOCTL_ALLOC_RAW_PORTAL, portal); + if (ret) { + perror("ioctl(DPAA_IOCTL_ALLOC_RAW_PORTAL)"); + return ret; + } + return 0; +} + +static int process_portal_free(struct dpaa_ioctl_raw_portal *portal) +{ + int ret = check_fd(); + + if (ret) + return ret; + + ret = ioctl(fd, DPAA_IOCTL_FREE_RAW_PORTAL, portal); + if (ret) { + perror("ioctl(DPAA_IOCTL_FREE_RAW_PORTAL)"); + return ret; + } + return 0; +} + +int qman_allocate_raw_portal(struct dpaa_raw_portal *portal) +{ + struct dpaa_ioctl_raw_portal input; + int ret; + + input.type = dpaa_portal_qman; + input.index = portal->index; + input.enable_stash = portal->enable_stash; + input.cpu = portal->cpu; + input.cache = portal->cache; + input.window = portal->window; + input.sdest = portal->sdest; + + ret = process_portal_allocate(&input); + if (ret) + return ret; + portal->index = input.index; + portal->cinh = input.cinh; + portal->cena = input.cena; + return 0; +} + +int qman_free_raw_portal(struct dpaa_raw_portal *portal) +{ + struct dpaa_ioctl_raw_portal input; + + input.type = dpaa_portal_qman; + input.index = portal->index; + input.cinh = portal->cinh; + input.cena = portal->cena; + + return process_portal_free(&input); +} + +int bman_allocate_raw_portal(struct dpaa_raw_portal *portal) +{ + struct dpaa_ioctl_raw_portal input; + int ret; + + input.type = dpaa_portal_bman; + input.index = portal->index; + input.enable_stash = 0; + + ret = process_portal_allocate(&input); + if (ret) + return ret; + portal->index = input.index; + portal->cinh = input.cinh; + portal->cena = input.cena; + return 0; +} + +int bman_free_raw_portal(struct dpaa_raw_portal *portal) +{ + struct dpaa_ioctl_raw_portal input; + + input.type = dpaa_portal_bman; + input.index = portal->index; + input.cinh = portal->cinh; + input.cena = portal->cena; + + return process_portal_free(&input); +} diff --git a/drivers/bus/dpaa/include/fsl_usd.h b/drivers/bus/dpaa/include/fsl_usd.h new file mode 100644 index 0000000..4ff48c6 --- /dev/null +++ b/drivers/bus/dpaa/include/fsl_usd.h @@ -0,0 +1,88 @@ +/*- + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * BSD LICENSE + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * GPL LICENSE SUMMARY + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_USD_H +#define __FSL_USD_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define QBMAN_ANY_PORTAL_IDX 0xffffffff + +/* Obtain and free raw (unitialized) portals */ + +struct dpaa_raw_portal { + /* inputs */ + + /* set to non zero to turn on stashing */ + uint8_t enable_stash; + /* Stashing attributes for the portal */ + uint32_t cpu; + uint32_t cache; + uint32_t window; + + /* Specifies the stash request queue this portal should use */ + uint8_t sdest; + + /* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX + * for don't care. The portal index will be populated by the + * driver when the ioctl() successfully completes. + */ + uint32_t index; + + /* outputs */ + uint64_t cinh; + uint64_t cena; +}; + +int qman_allocate_raw_portal(struct dpaa_raw_portal *portal); +int qman_free_raw_portal(struct dpaa_raw_portal *portal); + +int bman_allocate_raw_portal(struct dpaa_raw_portal *portal); +int bman_free_raw_portal(struct dpaa_raw_portal *portal); + +#ifdef __cplusplus +} +#endif + +#endif /* __FSL_USD_H */ diff --git a/drivers/bus/dpaa/include/process.h b/drivers/bus/dpaa/include/process.h new file mode 100644 index 0000000..989ddcd --- /dev/null +++ b/drivers/bus/dpaa/include/process.h @@ -0,0 +1,107 @@ +/*- + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * BSD LICENSE + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * GPL LICENSE SUMMARY + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PROCESS_H +#define __PROCESS_H + +#include + +/* The process device underlies process-wide user/kernel interactions, such as + * mapping dma_mem memory and providing accompanying ioctl()s. (This isn't used + * for portals, which use one UIO device each.). + */ +#define PROCESS_PATH "/dev/fsl-usdpaa" + +/* Allocation of resource IDs uses a generic interface. This enum is used to + * distinguish between the type of underlying object being manipulated. + */ +enum dpaa_id_type { + dpaa_id_fqid, + dpaa_id_bpid, + dpaa_id_qpool, + dpaa_id_cgrid, + dpaa_id_max /* <-- not a valid type, represents the number of types */ +}; + +int process_alloc(enum dpaa_id_type id_type, uint32_t *base, uint32_t num, + uint32_t align, int partial); +void process_release(enum dpaa_id_type id_type, uint32_t base, uint32_t num); + +int process_reserve(enum dpaa_id_type id_type, uint32_t base, uint32_t num); + +/* Mapping and using QMan/BMan portals */ +enum dpaa_portal_type { + dpaa_portal_qman, + dpaa_portal_bman, +}; + +struct dpaa_ioctl_portal_map { + /* Input parameter, is a qman or bman portal required. */ + enum dpaa_portal_type type; + /* Specifes a specific portal index to map or 0xffffffff + * for don't care. + */ + uint32_t index; + + /* Return value if the map succeeds, this gives the mapped + * cache-inhibited (cinh) and cache-enabled (cena) addresses. + */ + struct dpaa_portal_map { + void *cinh; + void *cena; + } addr; + /* Qman-specific return values */ + u16 channel; + uint32_t pools; +}; + +int process_portal_map(struct dpaa_ioctl_portal_map *params); +int process_portal_unmap(struct dpaa_portal_map *map); + +struct dpaa_ioctl_irq_map { + enum dpaa_portal_type type; /* Type of portal to map */ + int fd; /* File descriptor that contains the portal */ + void *portal_cinh; /* Cache inhibited area to identify the portal */ +}; + +int process_portal_irq_map(int fd, struct dpaa_ioctl_irq_map *irq); +int process_portal_irq_unmap(int fd); + +#endif /* __PROCESS_H */