diff mbox

[dpdk-dev,RFC] ring: relax alignment constraint on ring structure

Message ID 20170630142609.6180-1-olivier.matz@6wind.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers show

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Olivier Matz June 30, 2017, 2:26 p.m. UTC
The initial objective of
commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting")
was to add an empty cache line betwee, the producer and consumer
data (on platform with cache line size = 64B), preventing from
having them on adjacent cache lines.

Following discussion on the mailing list, it appears that this
also imposes an alignment constraint that is not required.

This patch removes the extra alignment constraint and adds the
empty cache lines using padding fields in the structure. The
size of rte_ring structure and the offset of the fields remain
the same on platforms with cache line size = 64B:

  rte_ring = 384
  rte_ring.name = 0
  rte_ring.flags = 32
  rte_ring.memzone = 40
  rte_ring.size = 48
  rte_ring.mask = 52
  rte_ring.prod = 128
  rte_ring.cons = 256

But it has an impact on platform where cache line size is 128B:

  rte_ring = 384        -> 768
  rte_ring.name = 0
  rte_ring.flags = 32
  rte_ring.memzone = 40
  rte_ring.size = 48
  rte_ring.mask = 52
  rte_ring.prod = 128   -> 256
  rte_ring.cons = 256   -> 512

Link: http://dpdk.org/dev/patchwork/patch/25039/
Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
---

I'm sending this patch to throw the discussion again, but since it
breaks the ABI on platform with cache lines = 128B, I think we should
follow the usual ABI breakage process.

If everybody agree, I'll send a notice and resend a similar patch after
17.08.

Olivier



 lib/librte_ring/rte_ring.h | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

Comments

Olivier Matz July 20, 2017, 8:52 a.m. UTC | #1
Hi,

On Fri, 30 Jun 2017 16:26:09 +0200, Olivier Matz <olivier.matz@6wind.com> wrote:
> The initial objective of
> commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting")
> was to add an empty cache line betwee, the producer and consumer
> data (on platform with cache line size = 64B), preventing from
> having them on adjacent cache lines.
> 
> Following discussion on the mailing list, it appears that this
> also imposes an alignment constraint that is not required.
> 
> This patch removes the extra alignment constraint and adds the
> empty cache lines using padding fields in the structure. The
> size of rte_ring structure and the offset of the fields remain
> the same on platforms with cache line size = 64B:
> 
>   rte_ring = 384
>   rte_ring.name = 0
>   rte_ring.flags = 32
>   rte_ring.memzone = 40
>   rte_ring.size = 48
>   rte_ring.mask = 52
>   rte_ring.prod = 128
>   rte_ring.cons = 256
> 
> But it has an impact on platform where cache line size is 128B:
> 
>   rte_ring = 384        -> 768
>   rte_ring.name = 0
>   rte_ring.flags = 32
>   rte_ring.memzone = 40
>   rte_ring.size = 48
>   rte_ring.mask = 52
>   rte_ring.prod = 128   -> 256
>   rte_ring.cons = 256   -> 512
> 
> Link: http://dpdk.org/dev/patchwork/patch/25039/
> Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
> ---
> 
> I'm sending this patch to throw the discussion again, but since it
> breaks the ABI on platform with cache lines = 128B, I think we should
> follow the usual ABI breakage process.
> 
> If everybody agree, I'll send a notice and resend a similar patch after
> 17.08.
> 

If there is no comment, I'll send a deprecation notice in the
coming days.

Thanks,
Olivier
diff mbox

Patch

diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h
index 1beb781b4..135b83df0 100644
--- a/lib/librte_ring/rte_ring.h
+++ b/lib/librte_ring/rte_ring.h
@@ -116,14 +116,6 @@  enum rte_ring_queue_behavior {
 
 struct rte_memzone; /* forward declaration, so as not to require memzone.h */
 
-#if RTE_CACHE_LINE_SIZE < 128
-#define PROD_ALIGN (RTE_CACHE_LINE_SIZE * 2)
-#define CONS_ALIGN (RTE_CACHE_LINE_SIZE * 2)
-#else
-#define PROD_ALIGN RTE_CACHE_LINE_SIZE
-#define CONS_ALIGN RTE_CACHE_LINE_SIZE
-#endif
-
 /* structure to hold a pair of head/tail values and other metadata */
 struct rte_ring_headtail {
 	volatile uint32_t head;  /**< Prod/consumer head. */
@@ -155,11 +147,15 @@  struct rte_ring {
 	uint32_t mask;           /**< Mask (size-1) of ring. */
 	uint32_t capacity;       /**< Usable size of ring */
 
+	char pad0 __rte_cache_aligned; /**< empty cache line */
+
 	/** Ring producer status. */
-	struct rte_ring_headtail prod __rte_aligned(PROD_ALIGN);
+	struct rte_ring_headtail prod __rte_cache_aligned;
+	char pad1 __rte_cache_aligned; /**< empty cache line */
 
 	/** Ring consumer status. */
-	struct rte_ring_headtail cons __rte_aligned(CONS_ALIGN);
+	struct rte_ring_headtail cons __rte_cache_aligned;
+	char pad2 __rte_cache_aligned; /**< empty cache line */
 };
 
 #define RING_F_SP_ENQ 0x0001 /**< The default enqueue is "single-producer". */