From patchwork Fri Sep 6 21:52:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Lakkireddy X-Patchwork-Id: 58910 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A8A621F4CB; Sat, 7 Sep 2019 00:00:09 +0200 (CEST) Received: from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id A047A1F4CA for ; Sat, 7 Sep 2019 00:00:07 +0200 (CEST) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id x86M02uD004215; Fri, 6 Sep 2019 15:00:03 -0700 From: Rahul Lakkireddy To: dev@dpdk.org Cc: nirranjan@chelsio.com Date: Sat, 7 Sep 2019 03:22:30 +0530 Message-Id: <1c5340dcd919f94af9fd63a9f6ef951eb5544a1e.1567799552.git.rahul.lakkireddy@chelsio.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 09/12] net/cxgbe: add devarg to control Tx coalescing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove compile time option to control Tx coalescing Latency vs Throughput behavior. Add tx_mode_latency devarg instead, to dynamically control Tx coalescing behavior. Signed-off-by: Rahul Lakkireddy --- config/common_base | 1 - doc/guides/nics/cxgbe.rst | 13 +++++++++---- drivers/net/cxgbe/base/adapter.h | 1 + drivers/net/cxgbe/cxgbe.h | 1 + drivers/net/cxgbe/cxgbe_ethdev.c | 3 ++- drivers/net/cxgbe/cxgbe_main.c | 3 +++ drivers/net/cxgbe/cxgbevf_ethdev.c | 1 + drivers/net/cxgbe/sge.c | 18 ++++++++---------- 8 files changed, 25 insertions(+), 16 deletions(-) diff --git a/config/common_base b/config/common_base index 43964de6d..48b134521 100644 --- a/config/common_base +++ b/config/common_base @@ -217,7 +217,6 @@ CONFIG_RTE_LIBRTE_BNXT_PMD=y # Compile burst-oriented Chelsio Terminator (CXGBE) PMD # CONFIG_RTE_LIBRTE_CXGBE_PMD=y -CONFIG_RTE_LIBRTE_CXGBE_TPUT=y # NXP DPAA Bus CONFIG_RTE_LIBRTE_DPAA_BUS=n diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst index 6e6767194..f15e0b90a 100644 --- a/doc/guides/nics/cxgbe.rst +++ b/doc/guides/nics/cxgbe.rst @@ -104,10 +104,6 @@ enabling debugging options may affect system performance. This controls compilation of both CXGBE and CXGBEVF PMD. -- ``CONFIG_RTE_LIBRTE_CXGBE_TPUT`` (default **y**) - - Toggle behavior to prefer Throughput or Latency. - Runtime Options ~~~~~~~~~~~~~~~ @@ -127,6 +123,15 @@ Common Runtime Options enabled, the outer VLAN tag is preserved in Q-in-Q packets. Otherwise, the outer VLAN tag is stripped in Q-in-Q packets. +- ``tx_mode_latency`` (default **0**) + + When set to 1, Tx doesn't wait for max number of packets to get + coalesced and sends the packets immediately at the end of the + current Tx burst. When set to 0, Tx waits across multiple Tx bursts + until the max number of packets have been coalesced. In this case, + Tx only sends the coalesced packets to hardware once the max + coalesce limit has been reached. + CXGBE VF Only Runtime Options ----------------------------- diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h index 68bd5a9cc..6a931ce97 100644 --- a/drivers/net/cxgbe/base/adapter.h +++ b/drivers/net/cxgbe/base/adapter.h @@ -302,6 +302,7 @@ TAILQ_HEAD(mbox_list, mbox_entry); struct adapter_devargs { bool keep_ovlan; bool force_link_up; + bool tx_mode_latency; }; struct adapter { diff --git a/drivers/net/cxgbe/cxgbe.h b/drivers/net/cxgbe/cxgbe.h index 3a50502b7..ed1be3559 100644 --- a/drivers/net/cxgbe/cxgbe.h +++ b/drivers/net/cxgbe/cxgbe.h @@ -52,6 +52,7 @@ /* Common PF and VF devargs */ #define CXGBE_DEVARG_CMN_KEEP_OVLAN "keep_ovlan" +#define CXGBE_DEVARG_CMN_TX_MODE_LATENCY "tx_mode_latency" /* VF only devargs */ #define CXGBE_DEVARG_VF_FORCE_LINK_UP "force_link_up" diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c index 8a2c2ca11..e99e5d057 100644 --- a/drivers/net/cxgbe/cxgbe_ethdev.c +++ b/drivers/net/cxgbe/cxgbe_ethdev.c @@ -1238,7 +1238,8 @@ RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, - CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "); + CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " + CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "); RTE_INIT(cxgbe_init_log) { diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c index 6a6137f06..23b74c754 100644 --- a/drivers/net/cxgbe/cxgbe_main.c +++ b/drivers/net/cxgbe/cxgbe_main.c @@ -672,6 +672,7 @@ void cxgbe_print_port_info(struct adapter *adap) static int check_devargs_handler(const char *key, const char *value, void *p) { if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) || + !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) || !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) { if (!strncmp(value, "1", 1)) { bool *dst_val = (bool *)p; @@ -728,6 +729,8 @@ void cxgbe_process_devargs(struct adapter *adap) { cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan, CXGBE_DEVARG_CMN_KEEP_OVLAN, 0); + cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency, + CXGBE_DEVARG_CMN_TX_MODE_LATENCY, 0); cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up, CXGBE_DEVARG_VF_FORCE_LINK_UP, 0); } diff --git a/drivers/net/cxgbe/cxgbevf_ethdev.c b/drivers/net/cxgbe/cxgbevf_ethdev.c index cc0938b43..4165ba986 100644 --- a/drivers/net/cxgbe/cxgbevf_ethdev.c +++ b/drivers/net/cxgbe/cxgbevf_ethdev.c @@ -213,4 +213,5 @@ RTE_PMD_REGISTER_PCI_TABLE(net_cxgbevf, cxgb4vf_pci_tbl); RTE_PMD_REGISTER_KMOD_DEP(net_cxgbevf, "* igb_uio | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_cxgbevf, CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " + CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " CXGBE_DEVARG_VF_FORCE_LINK_UP "=<0|1> "); diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c index bf3190211..0df870a41 100644 --- a/drivers/net/cxgbe/sge.c +++ b/drivers/net/cxgbe/sge.c @@ -1007,10 +1007,6 @@ static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq, unsigned int max_coal_pkt_num = is_pf4(adap) ? ETH_COALESCE_PKT_NUM : ETH_COALESCE_VF_PKT_NUM; -#ifdef RTE_LIBRTE_CXGBE_TPUT - RTE_SET_USED(nb_pkts); -#endif - if (q->coalesce.type == 0) { mc = (struct ulp_txpkt *)q->coalesce.ptr; mc->cmd_dest = htonl(V_ULPTX_CMD(4) | V_ULP_TXPKT_DEST(0) | @@ -1082,13 +1078,15 @@ static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq, sd->coalesce.sgl[idx & 1] = (struct ulptx_sgl *)(cpl + 1); sd->coalesce.idx = (idx & 1) + 1; - /* send the coaelsced work request if max reached */ - if (++q->coalesce.idx == max_coal_pkt_num -#ifndef RTE_LIBRTE_CXGBE_TPUT - || q->coalesce.idx >= nb_pkts -#endif - ) + /* Send the coalesced work request, only if max reached. However, + * if lower latency is preferred over throughput, then don't wait + * for coalescing the next Tx burst and send the packets now. + */ + q->coalesce.idx++; + if (q->coalesce.idx == max_coal_pkt_num || + (adap->devargs.tx_mode_latency && q->coalesce.idx >= nb_pkts)) ship_tx_pkt_coalesce_wr(adap, txq); + return 0; }