@@ -40,11 +40,11 @@ struct fsl_mc_io {
#define __arch_putq(v, a) (*(volatile uint64_t *)(a) = (v))
#define __arch_putq32(v, a) (*(volatile uint32_t *)(a) = (v))
#define readq(c) \
- ({ uint64_t __v = __arch_getq(c); __iormb(); __v; })
+ __extension__ ({ uint64_t __v = __arch_getq(c); __iormb(); __v; })
#define writeq(v, c) \
- ({ uint64_t __v = v; __iowmb(); __arch_putq(__v, c); __v; })
+ __extension__ ({ uint64_t __v = v; __iowmb(); __arch_putq(__v, c); __v; })
#define writeq32(v, c) \
- ({ uint32_t __v = v; __iowmb(); __arch_putq32(__v, c); __v; })
+ __extension__ ({ uint32_t __v = v; __iowmb(); __arch_putq32(__v, c); __v; })
#define ioread64(_p) readq(_p)
#define iowrite64(_v, _p) writeq(_v, _p)
#define iowrite32(_v, _p) writeq32(_v, _p)
@@ -30,21 +30,21 @@
#endif
#define roc_load_pair(val0, val1, addr) \
- ({ \
+ __extension__ ({ \
asm volatile("ldp %x[x0], %x[x1], [%x[p1]]" \
: [x0] "=r"(val0), [x1] "=r"(val1) \
: [p1] "r"(addr)); \
})
#define roc_store_pair(val0, val1, addr) \
- ({ \
+ __extension__ ({ \
asm volatile( \
"stp %x[x0], %x[x1], [%x[p1], #0]!" ::[x0] "r"(val0), \
[x1] "r"(val1), [p1] "r"(addr)); \
})
#define roc_prefetch_store_keep(ptr) \
- ({ asm volatile("prfm pstl1keep, [%x0]\n" : : "r"(ptr)); })
+ __extension__ ({ asm volatile("prfm pstl1keep, [%x0]\n" : : "r"(ptr)); })
#if defined(__clang__)
static __plt_always_inline void
@@ -82,7 +82,7 @@
/** Divide ceil */
#define PLT_DIV_CEIL(x, y) \
- ({ \
+ __extension__ ({ \
__typeof(x) __x = x; \
__typeof(y) __y = y; \
(__x + __y - 1) / __y; \
@@ -31,7 +31,7 @@ struct list_head n = { \
#define list_entry(node, type, member) \
(type *)((void *)node - offsetof(type, member))
#define list_empty(p) \
-({ \
+__extension__ ({ \
const struct list_head *__p298 = (p); \
((__p298->next == __p298) && (__p298->prev == __p298)); \
})
@@ -292,7 +292,7 @@ enum icp_qat_hw_cipher_convert {
#define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16
#define QAT_CIPHER_AEAD_AAD_SIZE_LE_BITPOS 0
#define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \
- ({ \
+ __extension__ ({ \
typeof(aad_size) aad_size1 = aad_size; \
(((((aad_size1) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \
QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) << \
@@ -139,7 +139,7 @@
* Extract particular combined mode crypto function from the 3D array.
*/
#define CRYPTO_GET_ALGO(order, cop, calg, aalg, keyl) \
-({ \
+__extension__ ({ \
crypto_func_tbl_t *func_tbl = \
(crypto_chain_order[(order)])[(cop)]; \
\
@@ -186,7 +186,7 @@
* Extract particular combined mode crypto function from the 3D array.
*/
#define CRYPTO_GET_KEY_SCHED(cop, calg, keyl) \
-({ \
+__extension__ ({ \
crypto_key_sched_tbl_t *ks_tbl = crypto_key_sched_dir[(cop)]; \
\
(calg >= CRYPTO_CIPHER_MAX) ? \
@@ -32,7 +32,7 @@
/* Macro for setting up a JD. The structure of the JD is common across all
* supported protocols, thus its structure is identical.
*/
-#define SEC_JD_INIT(descriptor) ({ \
+#define SEC_JD_INIT(descriptor) __extension__ ({ \
/* CTYPE = job descriptor \
* RSMS, DNR = 0
* ONE = 1
@@ -124,7 +124,7 @@
hisi_dma_write_queue(hw, qoff, tmp);
}
-#define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) ({ \
+#define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) __extension__ ({ \
uint32_t timeout = 0; \
while (timeout++ <= (timeout_us)) { \
(val) = hisi_dma_read_queue(hw, HISI_DMA_QUEUE_FSM_REG); \
@@ -96,14 +96,14 @@
/* ARM64 specific functions */
#if defined(RTE_ARCH_ARM64)
-#define ssovf_load_pair(val0, val1, addr) ({ \
+#define ssovf_load_pair(val0, val1, addr) __extension__ ({ \
asm volatile( \
"ldp %x[x0], %x[x1], [%x[p1]]" \
:[x0]"=r"(val0), [x1]"=r"(val1) \
:[p1]"r"(addr) \
); })
-#define ssovf_store_pair(val0, val1, addr) ({ \
+#define ssovf_store_pair(val0, val1, addr) __extension__ ({ \
asm volatile( \
"stp %x[x0], %x[x1], [%x[p1]]" \
::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
@@ -59,14 +59,14 @@
/* ARM64 specific functions */
#if defined(RTE_ARCH_ARM64)
-#define fpavf_load_pair(val0, val1, addr) ({ \
+#define fpavf_load_pair(val0, val1, addr) __extension__ ({ \
asm volatile( \
"ldp %x[x0], %x[x1], [%x[p1]]" \
:[x0]"=r"(val0), [x1]"=r"(val1) \
:[p1]"r"(addr) \
); })
-#define fpavf_store_pair(val0, val1, addr) ({ \
+#define fpavf_store_pair(val0, val1, addr) __extension__ ({ \
asm volatile( \
"stp %x[x0], %x[x1], [%x[p1]]" \
::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
@@ -44,8 +44,8 @@
/* Memory barrier macros */
#if defined(RTE_ARCH_ARM)
-#define dmb_st ({ asm volatile("dmb st" : : : "memory"); })
-#define dsb_st ({ asm volatile("dsb st" : : : "memory"); })
+#define dmb_st __extension__ ({ asm volatile("dmb st" : : : "memory"); })
+#define dsb_st __extension__ ({ asm volatile("dsb st" : : : "memory"); })
#else
#define dmb_st
#define dsb_st
@@ -4866,12 +4866,12 @@ static void bnxt_free_ctx_mem(struct bnxt *bp)
#define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
-#define min_t(type, x, y) ({ \
+#define min_t(type, x, y) __extension__ ({ \
type __min1 = (x); \
type __min2 = (y); \
__min1 < __min2 ? __min1 : __min2; })
-#define max_t(type, x, y) ({ \
+#define max_t(type, x, y) __extension__ ({ \
type __max1 = (x); \
type __max2 = (y); \
__max1 > __max2 ? __max1 : __max2; })
@@ -136,7 +136,7 @@
#define cxgbe_roundup(_p, _s) (((unsigned long)(_p) + (_s - 1)) & ~(_s - 1))
#ifndef container_of
-#define container_of(ptr, type, member) ({ \
+#define container_of(ptr, type, member) __extension__ ({ \
typeof(((type *)0)->member)(*__mptr) = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
#endif
@@ -141,9 +141,9 @@
#define ena_spinlock_t rte_spinlock_t
#define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&(spinlock))
#define ENA_SPINLOCK_LOCK(spinlock, flags) \
- ({(void)(flags); rte_spinlock_lock(&(spinlock)); })
+ __extension__ ({(void)(flags); rte_spinlock_lock(&(spinlock)); })
#define ENA_SPINLOCK_UNLOCK(spinlock, flags) \
- ({(void)(flags); rte_spinlock_unlock(&(spinlock)); })
+ __extension__ ({(void)(flags); rte_spinlock_unlock(&(spinlock)); })
#define ENA_SPINLOCK_DESTROY(spinlock) ((void)(spinlock))
typedef struct {
@@ -237,7 +237,7 @@
ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, \
mem_handle, RTE_CACHE_LINE_SIZE)
#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, mem_handle) \
- ({ ENA_TOUCH(size); ENA_TOUCH(phys); ENA_TOUCH(dmadev); \
+ __extension__ ({ ENA_TOUCH(size); ENA_TOUCH(phys); ENA_TOUCH(dmadev); \
rte_memzone_free(mem_handle); })
#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \
@@ -263,16 +263,16 @@
#define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
#define ENA_MEM_FREE(dmadev, ptr, size) \
- ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); })
+ __extension__ ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); })
#define ENA_DB_SYNC(mem_handle) ((void)mem_handle)
#define ENA_REG_WRITE32(bus, value, reg) \
- ({ (void)(bus); rte_write32((value), (reg)); })
+ __extension__ ({ (void)(bus); rte_write32((value), (reg)); })
#define ENA_REG_WRITE32_RELAXED(bus, value, reg) \
- ({ (void)(bus); rte_write32_relaxed((value), (reg)); })
+ __extension__ ({ (void)(bus); rte_write32_relaxed((value), (reg)); })
#define ENA_REG_READ32(bus, reg) \
- ({ (void)(bus); rte_read32_relaxed((reg)); })
+ __extension__ ({ (void)(bus); rte_read32_relaxed((reg)); })
#define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)
#define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)
@@ -459,7 +459,7 @@ struct ena_mp_body {
* calls to the same proxied function under the same lock.
*/
#define ENA_PROXY(a, f, ...) \
-({ \
+__extension__ ({ \
struct ena_adapter *_a = (a); \
struct timespec ts = { .tv_sec = ENA_MP_REQ_TMO }; \
struct ena_mp_body *req, *rsp; \
@@ -507,13 +507,13 @@ struct ena_mp_body {
*********************************************************************/
ENA_PROXY_DESC(ena_com_get_dev_basic_stats, ENA_MP_DEV_STATS_GET,
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(req);
ENA_TOUCH(ena_dev);
ENA_TOUCH(stats);
}),
-({
+__extension__ ({
ENA_TOUCH(rsp);
ENA_TOUCH(ena_dev);
if (stats != &adapter->basic_stats)
@@ -522,13 +522,13 @@ struct ena_mp_body {
struct ena_com_dev *ena_dev, struct ena_admin_basic_stats *stats);
ENA_PROXY_DESC(ena_com_get_eni_stats, ENA_MP_ENI_STATS_GET,
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(req);
ENA_TOUCH(ena_dev);
ENA_TOUCH(stats);
}),
-({
+__extension__ ({
ENA_TOUCH(rsp);
ENA_TOUCH(ena_dev);
if (stats != (struct ena_admin_eni_stats *)&adapter->metrics_stats)
@@ -537,12 +537,12 @@ struct ena_mp_body {
struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats);
ENA_PROXY_DESC(ena_com_set_dev_mtu, ENA_MP_MTU_SET,
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(ena_dev);
req->args.mtu = mtu;
}),
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(rsp);
ENA_TOUCH(ena_dev);
@@ -551,12 +551,12 @@ struct ena_mp_body {
struct ena_com_dev *ena_dev, int mtu);
ENA_PROXY_DESC(ena_com_indirect_table_set, ENA_MP_IND_TBL_SET,
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(req);
ENA_TOUCH(ena_dev);
}),
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(rsp);
ENA_TOUCH(ena_dev);
@@ -564,13 +564,13 @@ struct ena_mp_body {
struct ena_com_dev *ena_dev);
ENA_PROXY_DESC(ena_com_indirect_table_get, ENA_MP_IND_TBL_GET,
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(req);
ENA_TOUCH(ena_dev);
ENA_TOUCH(ind_tbl);
}),
-({
+__extension__ ({
ENA_TOUCH(rsp);
ENA_TOUCH(ena_dev);
if (ind_tbl != adapter->indirect_table)
@@ -580,14 +580,14 @@ struct ena_mp_body {
struct ena_com_dev *ena_dev, u32 *ind_tbl);
ENA_PROXY_DESC(ena_com_get_customer_metrics, ENA_MP_CUSTOMER_METRICS_GET,
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(req);
ENA_TOUCH(ena_dev);
ENA_TOUCH(buf);
ENA_TOUCH(buf_size);
}),
-({
+__extension__ ({
ENA_TOUCH(rsp);
ENA_TOUCH(ena_dev);
ENA_TOUCH(buf_size);
@@ -597,13 +597,13 @@ struct ena_mp_body {
struct ena_com_dev *ena_dev, char *buf, size_t buf_size);
ENA_PROXY_DESC(ena_com_get_ena_srd_info, ENA_MP_SRD_STATS_GET,
-({
+__extension__ ({
ENA_TOUCH(adapter);
ENA_TOUCH(req);
ENA_TOUCH(ena_dev);
ENA_TOUCH(info);
}),
-({
+__extension__ ({
ENA_TOUCH(rsp);
ENA_TOUCH(ena_dev);
if ((struct ena_stats_srd *)info != &adapter->srd_stats)
@@ -42,7 +42,7 @@
#define ENETFEC_MAX_Q 1
-#define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
+#define writel(v, p) __extension__ ({*(volatile unsigned int *)(p) = (v); })
#define readl(p) rte_read32(p)
struct bufdesc {
@@ -102,7 +102,7 @@
#endif
#ifndef do_div
-#define do_div(n, base) ({\
+#define do_div(n, base) __extension__ ({\
(n) = (n) / (base);\
})
#endif /* do_div */
@@ -46,7 +46,7 @@
#define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
#undef container_of
-#define container_of(ptr, type, member) ({ \
+#define container_of(ptr, type, member) __extension__ ({ \
typeof(((type *)0)->member)(*__mptr) = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
@@ -19,17 +19,17 @@
/* ARM64 specific functions */
#if defined(RTE_ARCH_ARM64)
-#define octeontx_prefetch_store_keep(_ptr) ({\
+#define octeontx_prefetch_store_keep(_ptr) __extension__ ({\
asm volatile("prfm pstl1keep, %a0\n" : : "p" (_ptr)); })
-#define octeontx_load_pair(val0, val1, addr) ({ \
+#define octeontx_load_pair(val0, val1, addr) __extension__ ({ \
asm volatile( \
"ldp %x[x0], %x[x1], [%x[p1]]" \
:[x0]"=r"(val0), [x1]"=r"(val1) \
:[p1]"r"(addr) \
); })
-#define octeontx_store_pair(val0, val1, addr) ({ \
+#define octeontx_store_pair(val0, val1, addr) __extension__ ({ \
asm volatile( \
"stp %x[x0], %x[x1], [%x[p1]]" \
::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
@@ -36,7 +36,7 @@
/* Byte Enables of the Internal memory access. These are interpred in BE */
#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \
- ({ typeof(size) size_ = (size); \
+ __extension__ ({ typeof(size) size_ = (size); \
(((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
#include "cbus/emac_mtip.h"
@@ -95,36 +95,36 @@
#define PMEM_SIZE 0x8000 /* TMU has less... */
#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
-#define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
+#define writel(v, p) __extension__ ({*(volatile unsigned int *)(p) = (v); })
#define readl(p) (*(const volatile unsigned int *)(p))
/* These check memory ranges from PE point of view/memory map */
#define IS_DMEM(addr, len) \
- ({ typeof(addr) addr_ = (addr); \
+ __extension__ ({ typeof(addr) addr_ = (addr); \
((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \
(((unsigned long)(addr_) + (len)) <= DMEM_END); })
#define IS_PMEM(addr, len) \
- ({ typeof(addr) addr_ = (addr); \
+ __extension__ ({ typeof(addr) addr_ = (addr); \
((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \
(((unsigned long)(addr_) + (len)) <= PMEM_END); })
#define IS_PE_LMEM(addr, len) \
- ({ typeof(addr) addr_ = (addr); \
+ __extension__ ({ typeof(addr) addr_ = (addr); \
((unsigned long)(addr_) >= \
PE_LMEM_BASE_ADDR) && \
(((unsigned long)(addr_) + \
(len)) <= PE_LMEM_END); })
#define IS_PFE_LMEM(addr, len) \
- ({ typeof(addr) addr_ = (addr); \
+ __extension__ ({ typeof(addr) addr_ = (addr); \
((unsigned long)(addr_) >= \
CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \
(((unsigned long)(addr_) + (len)) <= \
CBUS_VIRT_TO_PFE(LMEM_END)); })
#define __IS_PHYS_DDR(addr, len) \
- ({ typeof(addr) addr_ = (addr); \
+ __extension__ ({ typeof(addr) addr_ = (addr); \
((unsigned long)(addr_) >= \
DDR_PHYS_BASE_ADDR) && \
(((unsigned long)(addr_) + (len)) <= \
@@ -162,7 +162,7 @@ static int BPF_FUNC(map_update_elem, void *map, const void *key,
#ifndef printt
# define printt(fmt, ...) \
- ({ \
+ __extension__ ({ \
char ____fmt[] = fmt; \
trace_printk(____fmt, sizeof(____fmt), ##__VA_ARGS__); \
})
@@ -55,11 +55,11 @@
/* ARM64 specific functions */
#if defined(RTE_ARCH_ARM64)
-#define nicvf_prefetch_store_keep(_ptr) ({\
+#define nicvf_prefetch_store_keep(_ptr) __extension__ ({\
asm volatile("prfm pstl1keep, [%x0]\n" : : "r" (_ptr)); })
-#define NICVF_LOAD_PAIR(reg1, reg2, addr) ({ \
+#define NICVF_LOAD_PAIR(reg1, reg2, addr) __extension__ ({ \
asm volatile( \
"ldp %x[x1], %x[x0], [%x[p1]]" \
: [x1]"=r"(reg1), [x0]"=r"(reg2)\
@@ -172,7 +172,7 @@ static inline u64 REVERT_BIT_MASK64(u64 mask)
/* Check whether an address is broadcast. */
#define TXGBE_IS_BROADCAST(address) \
- ({typeof(address)addr = (address); \
+ __extension__ ({typeof(address)addr = (address); \
(((u8 *)(addr))[0] == ((u8)0xff)) && \
(((u8 *)(addr))[1] == ((u8)0xff)); })
@@ -66,7 +66,7 @@ struct afu_rawdev {
#define MHZ(f) ((f) * 1000000)
#define dsm_poll_timeout(addr, val, cond, invl, timeout) \
-({ \
+__extension__ ({ \
uint64_t __wait = 0; \
uint64_t __invl = (invl); \
uint64_t __timeout = (timeout); \
@@ -8,7 +8,7 @@
#include "opae_osdep.h"
#undef container_of
-#define container_of(ptr, type, member) ({ \
+#define container_of(ptr, type, member) __extension__ ({ \
typeof(((type *)0)->member)(*__mptr) = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
@@ -36,7 +36,7 @@
* by polling with given interval and timeout.
*/
#define fpga_wait_register_field(_field, _expect, _reg_addr, _timeout, _invl)\
-({ \
+__extension__ ({ \
int wait = 0; \
int ret = -ETIMEDOUT; \
typeof(_expect) value; \
@@ -81,7 +81,7 @@ struct uuid {
#define opae_memset(a, b, c) memset((a), (b), (c))
#define readx_poll_timeout(op, val, cond, invl, timeout, args...) \
-({ \
+__extension__ ({ \
unsigned long __wait = 0; \
unsigned long __invl = (invl); \
unsigned long __timeout = (timeout); \
@@ -107,7 +107,7 @@ struct uuid {
readx_poll_timeout(opae_readb, val, cond, invl, timeout, addr)
#define opae_max10_read_poll_timeout(dev, addr, value, cond, invl, timeout) \
-({ \
+__extension__ ({ \
int __ret, __tmp; \
__tmp = readx_poll_timeout(max10_sys_read, __ret, __ret || (cond), \
invl, timeout, (dev), (addr), &(value)); \
@@ -24,7 +24,7 @@
#define SPI_REG_BYTES 4
#define INIT_SPI_TRAN_HEADER(trans_type, size, address) \
-({ \
+__extension__ ({ \
header.trans_type = trans_type; \
header.reserve = 0; \
header.size = cpu_to_be16(size); \
@@ -41,12 +41,12 @@
#define min(a, b) RTE_MIN(a, b)
#define max(a, b) RTE_MAX(a, b)
-#define min_t(type, x, y) ({ \
+#define min_t(type, x, y) __extension__ ({ \
type __min1 = (x); \
type __min2 = (y); \
__min1 < __min2 ? __min1 : __min2; })
-#define max_t(type, x, y) ({ \
+#define max_t(type, x, y) __extension__ ({ \
type __max1 = (x); \
type __max2 = (y); \
__max1 > __max2 ? __max1 : __max2; })