diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c
index 7e388b7569..c3b087c52e 100644
--- a/drivers/net/ice/ice_rxtx_vec_avx512.c
+++ b/drivers/net/ice/ice_rxtx_vec_avx512.c
@@ -16,125 +16,7 @@
 static __rte_always_inline void
 ice_rxq_rearm(struct ice_rx_queue *rxq)
 {
-	int i;
-	uint16_t rx_id;
-	volatile union ice_rx_flex_desc *rxdp;
-	struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
-	struct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,
-			rte_lcore_id());
-
-	rxdp = rxq->rx_ring + rxq->rxrearm_start;
-
-	if (unlikely(!cache))
-		return ice_rxq_rearm_common(rxq, true);
-
-	/* We need to pull 'n' more MBUFs into the software ring */
-	if (cache->len < ICE_RXQ_REARM_THRESH) {
-		uint32_t req = ICE_RXQ_REARM_THRESH + (cache->size -
-				cache->len);
-
-		int ret = rte_mempool_ops_dequeue_bulk(rxq->mp,
-				&cache->objs[cache->len], req);
-		if (ret == 0) {
-			cache->len += req;
-		} else {
-			if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
-			    rxq->nb_rx_desc) {
-				__m128i dma_addr0;
-
-				dma_addr0 = _mm_setzero_si128();
-				for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
-					rxep[i].mbuf = &rxq->fake_mbuf;
-					_mm_store_si128
-						((__m128i *)&rxdp[i].read,
-							dma_addr0);
-				}
-			}
-			rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
-				ICE_RXQ_REARM_THRESH;
-			return;
-		}
-	}
-
-#if RTE_IOVA_AS_PA
-	const __m512i iova_offsets =  _mm512_set1_epi64
-		(offsetof(struct rte_mbuf, buf_iova));
-#else
-	const __m512i iova_offsets =  _mm512_set1_epi64
-		(offsetof(struct rte_mbuf, buf_addr));
-#endif
-	const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
-
-#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
-	/* shuffle the iova into correct slots. Values 4-7 will contain
-	 * zeros, so use 7 for a zero-value.
-	 */
-	const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
-#else
-	const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
-#endif
-
-	/* fill up the rxd in vector, process 8 mbufs in one loop */
-	for (i = 0; i < ICE_RXQ_REARM_THRESH / 8; i++) {
-		const __m512i mbuf_ptrs = _mm512_loadu_si512
-			(&cache->objs[cache->len - 8]);
-		_mm512_store_si512(rxep, mbuf_ptrs);
-
-		/* gather iova of mbuf0-7 into one zmm reg */
-		const __m512i iova_base_addrs = _mm512_i64gather_epi64
-			(_mm512_add_epi64(mbuf_ptrs, iova_offsets),
-				0, /* base */
-				1  /* scale */);
-		const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
-				headroom);
-#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
-		const __m512i iovas0 = _mm512_castsi256_si512
-			(_mm512_extracti64x4_epi64(iova_addrs, 0));
-		const __m512i iovas1 = _mm512_castsi256_si512
-			(_mm512_extracti64x4_epi64(iova_addrs, 1));
-
-		/* permute leaves iova 2-3 in hdr_addr of desc 0-1
-		 * but these are ignored by driver since header split not
-		 * enabled. Similarly for desc 4 & 5.
-		 */
-		const __m512i desc0_1 = _mm512_permutexvar_epi64
-			(permute_idx, iovas0);
-		const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
-
-		const __m512i desc4_5 = _mm512_permutexvar_epi64
-			(permute_idx, iovas1);
-		const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
-
-		_mm512_store_si512((void *)rxdp, desc0_1);
-		_mm512_store_si512((void *)(rxdp + 2), desc2_3);
-		_mm512_store_si512((void *)(rxdp + 4), desc4_5);
-		_mm512_store_si512((void *)(rxdp + 6), desc6_7);
-#else
-		/* permute leaves iova 4-7 in hdr_addr of desc 0-3
-		 * but these are ignored by driver since header split not
-		 * enabled.
-		 */
-		const __m512i desc0_3 = _mm512_permutexvar_epi64
-			(permute_idx, iova_addrs);
-		const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
-
-		_mm512_store_si512((void *)rxdp, desc0_3);
-		_mm512_store_si512((void *)(rxdp + 4), desc4_7);
-#endif
-		rxep += 8, rxdp += 8, cache->len -= 8;
-	}
-
-	rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
-	if (rxq->rxrearm_start >= rxq->nb_rx_desc)
-		rxq->rxrearm_start = 0;
-
-	rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
-
-	rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
-			     (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
-
-	/* Update the tail pointer on the NIC */
-	ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
+	ice_rxq_rearm_common(rxq, true);
 }
 
 static inline __m256i
