[v4,05/14] baseband/acc: add HW register definitions for ACC200
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Commit Message
Add registers list and structure to access the device.
Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc/acc200_pf_enum.h | 108 ++++++++++++++++++++++
drivers/baseband/acc/acc200_pmd.h | 163 ++++++++++++++++++++++++++++++++++
drivers/baseband/acc/acc200_vf_enum.h | 83 +++++++++++++++++
drivers/baseband/acc/rte_acc200_pmd.c | 2 +
4 files changed, 356 insertions(+)
create mode 100644 drivers/baseband/acc/acc200_pf_enum.h
create mode 100644 drivers/baseband/acc/acc200_vf_enum.h
Comments
On 9/22/22 02:27, Nic Chautru wrote:
> Add registers list and structure to access the device.
>
> Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc/acc200_pf_enum.h | 108 ++++++++++++++++++++++
> drivers/baseband/acc/acc200_pmd.h | 163 ++++++++++++++++++++++++++++++++++
> drivers/baseband/acc/acc200_vf_enum.h | 83 +++++++++++++++++
> drivers/baseband/acc/rte_acc200_pmd.c | 2 +
> 4 files changed, 356 insertions(+)
> create mode 100644 drivers/baseband/acc/acc200_pf_enum.h
> create mode 100644 drivers/baseband/acc/acc200_vf_enum.h
>
> diff --git a/drivers/baseband/acc/acc200_pf_enum.h b/drivers/baseband/acc/acc200_pf_enum.h
> new file mode 100644
> index 0000000..e52d8f5
> --- /dev/null
> +++ b/drivers/baseband/acc/acc200_pf_enum.h
> @@ -0,0 +1,108 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2021 Intel Corporation
> + */
> +
> +#ifndef ACC200_PF_ENUM_H
> +#define ACC200_PF_ENUM_H
> +
> +/*
> + * ACC200 Register mapping on PF BAR0
> + * This is automatically generated from RDL, format may change with new RDL
> + * Release.
> + * Variable names are as is
> + */
> +enum {
> + HWPfQmgrEgressQueuesTemplate = 0x0007FC00,
> + HWPfQmgrIngressAq = 0x00080000,
> + HWPfQmgrDepthLog2Grp = 0x00A00200,
> + HWPfQmgrTholdGrp = 0x00A00300,
> + HWPfQmgrGrpTmplateReg0Indx = 0x00A00600,
> + HWPfQmgrGrpTmplateReg1Indx = 0x00A00700,
> + HWPfQmgrGrpTmplateReg2indx = 0x00A00800,
> + HWPfQmgrGrpTmplateReg3Indx = 0x00A00900,
> + HWPfQmgrGrpTmplateReg4Indx = 0x00A00A00,
> + HWPfQmgrVfBaseAddr = 0x00A01000,
> + HWPfQmgrArbQDepthGrp = 0x00A02F00,
> + HWPfQmgrGrpFunction0 = 0x00A02F40,
> + HWPfQmgrGrpFunction1 = 0x00A02F44,
> + HWPfQmgrGrpPriority = 0x00A02F48,
> + HWPfQmgrAqEnableVf = 0x00A10000,
> + HWPfQmgrRingSizeVf = 0x00A20004,
> + HWPfQmgrGrpDepthLog20Vf = 0x00A20008,
> + HWPfQmgrGrpDepthLog21Vf = 0x00A2000C,
> + HWPfFabricM2iBufferReg = 0x00B30000,
> + HWPfFabricI2Mdma_weight = 0x00B31044,
> + HwPfFecUl5gIbDebugReg = 0x00B40200,
> + HWPfFftConfig0 = 0x00B58004,
> + HWPfFftRamPageAccess = 0x00B5800C,
> + HWPfFftRamOff = 0x00B58800,
> + HWPfDmaConfig0Reg = 0x00B80000,
> + HWPfDmaConfig1Reg = 0x00B80004,
> + HWPfDmaQmgrAddrReg = 0x00B80008,
> + HWPfDmaAxcacheReg = 0x00B80010,
> + HWPfDmaAxiControl = 0x00B8002C,
> + HWPfDmaQmanen = 0x00B80040,
> + HWPfDma4gdlIbThld = 0x00B800CC,
> + HWPfDmaCfgRrespBresp = 0x00B80814,
> + HWPfDmaDescriptorSignatuture = 0x00B80868,
> + HWPfDmaErrorDetectionEn = 0x00B80870,
> + HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020,
> + HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024,
> + HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028,
> + HWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C,
> + HWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040,
> + HWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044,
> + HWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048,
> + HWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C,
> + HWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060,
> + HWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064,
> + HWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068,
> + HWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C,
> + HWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080,
> + HWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084,
> + HWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088,
> + HWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C,
> + HWPDmaFftDescBaseLoRegVf = 0x00B880A0,
> + HWPDmaFftDescBaseHiRegVf = 0x00B880A4,
> + HWPDmaFftRespPtrLoRegVf = 0x00B880A8,
> + HWPDmaFftRespPtrHiRegVf = 0x00B880AC,
> + HWPfQosmonAEvalOverflow0 = 0x00B90008,
> + HWPfPermonACntrlRegVf = 0x00B98000,
> + HWPfQosmonBEvalOverflow0 = 0x00BA0008,
> + HWPfPermonBCntrlRegVf = 0x00BA8000,
> + HWPfPermonCCntrlRegVf = 0x00BB8000,
> + HWPfHiInfoRingBaseLoRegPf = 0x00C84014,
> + HWPfHiInfoRingBaseHiRegPf = 0x00C84018,
> + HWPfHiInfoRingPointerRegPf = 0x00C8401C,
> + HWPfHiInfoRingIntWrEnRegPf = 0x00C84020,
> + HWPfHiBlockTransmitOnErrorEn = 0x00C84038,
> + HWPfHiCfgMsiIntWrEnRegPf = 0x00C84040,
> + HWPfHiMsixVectorMapperPf = 0x00C84060,
> + HWPfHiPfMode = 0x00C84108,
> + HWPfHiClkGateHystReg = 0x00C8410C,
> + HWPfHiMsiDropEnableReg = 0x00C84114,
> + HWPfHiSectionPowerGatingReq = 0x00C84128,
> + HWPfHiSectionPowerGatingAck = 0x00C8412C,
> +};
> +
> +/* TIP PF Interrupt numbers */
> +enum {
> + ACC200_PF_INT_QMGR_AQ_OVERFLOW = 0,
> + ACC200_PF_INT_DOORBELL_VF_2_PF = 1,
> + ACC200_PF_INT_ILLEGAL_FORMAT = 2,
> + ACC200_PF_INT_QMGR_DISABLED_ACCESS = 3,
> + ACC200_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
> + ACC200_PF_INT_DMA_DL_DESC_IRQ = 5,
> + ACC200_PF_INT_DMA_UL_DESC_IRQ = 6,
> + ACC200_PF_INT_DMA_FFT_DESC_IRQ = 7,
> + ACC200_PF_INT_DMA_UL5G_DESC_IRQ = 8,
> + ACC200_PF_INT_DMA_DL5G_DESC_IRQ = 9,
> + ACC200_PF_INT_DMA_MLD_DESC_IRQ = 10,
> + ACC200_PF_INT_ARAM_ECC_1BIT_ERR = 11,
> + ACC200_PF_INT_PARITY_ERR = 12,
> + ACC200_PF_INT_QMGR_ERR = 13,
> + ACC200_PF_INT_INT_REQ_OVERFLOW = 14,
> + ACC200_PF_INT_APB_TIMEOUT = 15,
> +};
> +
> +#endif /* ACC200_PF_ENUM_H */
> diff --git a/drivers/baseband/acc/acc200_pmd.h b/drivers/baseband/acc/acc200_pmd.h
> index aaa6b77..9df1f50 100644
> --- a/drivers/baseband/acc/acc200_pmd.h
> +++ b/drivers/baseband/acc/acc200_pmd.h
> @@ -6,6 +6,8 @@
> #define _RTE_ACC200_PMD_H_
>
> #include "acc_common.h"
> +#include "acc200_pf_enum.h"
> +#include "acc200_vf_enum.h"
>
> /* Helper macro for logging */
> #define rte_bbdev_log(level, fmt, ...) \
> @@ -29,4 +31,165 @@
> #define RTE_ACC200_PF_DEVICE_ID (0x57C0)
> #define RTE_ACC200_VF_DEVICE_ID (0x57C1)
>
> +#define ACC200_MAX_PF_MSIX (256+32)
> +#define ACC200_MAX_VF_MSIX (256+7)
> +
> +/* Values used in writing to the registers */
> +#define ACC200_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
> +
> +/* Number of Virtual Functions ACC200 supports */
> +#define ACC200_NUM_VFS 16
> +#define ACC200_NUM_QGRPS 16
> +#define ACC200_NUM_AQS 16
> +
> +#define ACC200_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
> +#define ACC200_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
> +#define ACC200_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)
> +
> +/* Mapping of signals for the available engines */
> +#define ACC200_SIG_UL_5G 0
> +#define ACC200_SIG_UL_5G_LAST 4
> +#define ACC200_SIG_DL_5G 10
> +#define ACC200_SIG_DL_5G_LAST 11
> +#define ACC200_SIG_UL_4G 12
> +#define ACC200_SIG_UL_4G_LAST 16
> +#define ACC200_SIG_DL_4G 21
> +#define ACC200_SIG_DL_4G_LAST 23
> +#define ACC200_SIG_FFT 24
> +#define ACC200_SIG_FFT_LAST 24
> +
> +#define ACC200_NUM_ACCS 5 /* FIXMEFFT */
> +
> +/* ACC200 Configuration */
> +#define ACC200_FABRIC_MODE 0x8000103
> +#define ACC200_CFG_DMA_ERROR 0x3DF
> +#define ACC200_CFG_AXI_CACHE 0x11
> +#define ACC200_CFG_QMGR_HI_P 0x0F0F
> +#define ACC200_RESET_HARD 0x1FF
> +#define ACC200_ENGINES_MAX 9
> +#define ACC200_GPEX_AXIMAP_NUM 17
> +#define ACC200_CLOCK_GATING_EN 0x30000
> +#define ACC200_FFT_CFG_0 0x2001
> +#define ACC200_FFT_RAM_EN 0x80008000
> +#define ACC200_FFT_RAM_DIS 0x0
> +#define ACC200_FFT_RAM_SIZE 512
> +#define ACC200_CLK_EN 0x00010A01
> +#define ACC200_CLK_DIS 0x01F10A01
> +#define ACC200_PG_MASK_0 0x1F
> +#define ACC200_PG_MASK_1 0xF
> +#define ACC200_PG_MASK_2 0x1
> +#define ACC200_PG_MASK_3 0x0
> +#define ACC200_PG_MASK_FFT 1
> +#define ACC200_PG_MASK_4GUL 4
> +#define ACC200_PG_MASK_5GUL 8
> +#define ACC200_STATUS_WAIT 10
> +#define ACC200_STATUS_TO 100
> +
> +struct acc200_registry_addr {
> + unsigned int dma_ring_dl5g_hi;
> + unsigned int dma_ring_dl5g_lo;
> + unsigned int dma_ring_ul5g_hi;
> + unsigned int dma_ring_ul5g_lo;
> + unsigned int dma_ring_dl4g_hi;
> + unsigned int dma_ring_dl4g_lo;
> + unsigned int dma_ring_ul4g_hi;
> + unsigned int dma_ring_ul4g_lo;
> + unsigned int dma_ring_fft_hi;
> + unsigned int dma_ring_fft_lo;
> + unsigned int ring_size;
> + unsigned int info_ring_hi;
> + unsigned int info_ring_lo;
> + unsigned int info_ring_en;
> + unsigned int info_ring_ptr;
> + unsigned int tail_ptrs_dl5g_hi;
> + unsigned int tail_ptrs_dl5g_lo;
> + unsigned int tail_ptrs_ul5g_hi;
> + unsigned int tail_ptrs_ul5g_lo;
> + unsigned int tail_ptrs_dl4g_hi;
> + unsigned int tail_ptrs_dl4g_lo;
> + unsigned int tail_ptrs_ul4g_hi;
> + unsigned int tail_ptrs_ul4g_lo;
> + unsigned int tail_ptrs_fft_hi;
> + unsigned int tail_ptrs_fft_lo;
> + unsigned int depth_log0_offset;
> + unsigned int depth_log1_offset;
> + unsigned int qman_group_func;
> + unsigned int hi_mode;
> + unsigned int pmon_ctrl_a;
> + unsigned int pmon_ctrl_b;
> + unsigned int pmon_ctrl_c;
> +};
> +
> +/* Structure holding registry addresses for PF */
> +static const struct acc200_registry_addr pf_reg_addr = {
> + .dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
> + .dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
> + .dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
> + .dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
> + .dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
> + .dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
> + .dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
> + .dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
> + .dma_ring_fft_hi = HWPDmaFftDescBaseHiRegVf,
> + .dma_ring_fft_lo = HWPDmaFftDescBaseLoRegVf,
> + .ring_size = HWPfQmgrRingSizeVf,
> + .info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
> + .info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
> + .info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
> + .info_ring_ptr = HWPfHiInfoRingPointerRegPf,
> + .tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
> + .tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
> + .tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
> + .tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
> + .tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
> + .tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
> + .tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
> + .tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
> + .tail_ptrs_fft_hi = HWPDmaFftRespPtrHiRegVf,
> + .tail_ptrs_fft_lo = HWPDmaFftRespPtrLoRegVf,
> + .depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
> + .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
> + .qman_group_func = HWPfQmgrGrpFunction0,
> + .hi_mode = HWPfHiMsixVectorMapperPf,
> + .pmon_ctrl_a = HWPfPermonACntrlRegVf,
> + .pmon_ctrl_b = HWPfPermonBCntrlRegVf,
> + .pmon_ctrl_c = HWPfPermonCCntrlRegVf,
> +};
> +
> +/* Structure holding registry addresses for VF */
> +static const struct acc200_registry_addr vf_reg_addr = {
> + .dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
> + .dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
> + .dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
> + .dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
> + .dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
> + .dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
> + .dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
> + .dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
> + .dma_ring_fft_hi = HWVfDmaFftDescBaseHiRegVf,
> + .dma_ring_fft_lo = HWVfDmaFftDescBaseLoRegVf,
> + .ring_size = HWVfQmgrRingSizeVf,
> + .info_ring_hi = HWVfHiInfoRingBaseHiVf,
> + .info_ring_lo = HWVfHiInfoRingBaseLoVf,
> + .info_ring_en = HWVfHiInfoRingIntWrEnVf,
> + .info_ring_ptr = HWVfHiInfoRingPointerVf,
> + .tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
> + .tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
> + .tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
> + .tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
> + .tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
> + .tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
> + .tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
> + .tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
> + .tail_ptrs_fft_hi = HWVfDmaFftRespPtrHiRegVf,
> + .tail_ptrs_fft_lo = HWVfDmaFftRespPtrLoRegVf,
> + .depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
> + .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
> + .qman_group_func = HWVfQmgrGrpFunction0Vf,
> + .hi_mode = HWVfHiMsixVectorMapperVf,
> + .pmon_ctrl_a = HWVfPmACntrlRegVf,
> + .pmon_ctrl_b = HWVfPmBCntrlRegVf,
> + .pmon_ctrl_c = HWVfPmCCntrlRegVf,
> +};
> +
> #endif /* _RTE_ACC200_PMD_H_ */
> diff --git a/drivers/baseband/acc/acc200_vf_enum.h b/drivers/baseband/acc/acc200_vf_enum.h
> new file mode 100644
> index 0000000..0d35420
> --- /dev/null
> +++ b/drivers/baseband/acc/acc200_vf_enum.h
> @@ -0,0 +1,83 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2021 Intel Corporation
> + */
> +
> +#ifndef ACC200_VF_ENUM_H
> +#define ACC200_VF_ENUM_H
> +
> +/*
> + * ACC200 Register mapping on VF BAR0
> + * This is automatically generated from RDL, format may change with new RDL
> + */
> +enum {
> + HWVfQmgrIngressAq = 0x00000000,
> + HWVfHiVfToPfDbellVf = 0x00000800,
> + HWVfHiPfToVfDbellVf = 0x00000808,
> + HWVfHiInfoRingBaseLoVf = 0x00000810,
> + HWVfHiInfoRingBaseHiVf = 0x00000814,
> + HWVfHiInfoRingPointerVf = 0x00000818,
> + HWVfHiInfoRingIntWrEnVf = 0x00000820,
> + HWVfHiInfoRingPf2VfWrEnVf = 0x00000824,
> + HWVfHiMsixVectorMapperVf = 0x00000860,
> + HWVfDmaFec5GulDescBaseLoRegVf = 0x00000920,
> + HWVfDmaFec5GulDescBaseHiRegVf = 0x00000924,
> + HWVfDmaFec5GulRespPtrLoRegVf = 0x00000928,
> + HWVfDmaFec5GulRespPtrHiRegVf = 0x0000092C,
> + HWVfDmaFec5GdlDescBaseLoRegVf = 0x00000940,
> + HWVfDmaFec5GdlDescBaseHiRegVf = 0x00000944,
> + HWVfDmaFec5GdlRespPtrLoRegVf = 0x00000948,
> + HWVfDmaFec5GdlRespPtrHiRegVf = 0x0000094C,
> + HWVfDmaFec4GulDescBaseLoRegVf = 0x00000960,
> + HWVfDmaFec4GulDescBaseHiRegVf = 0x00000964,
> + HWVfDmaFec4GulRespPtrLoRegVf = 0x00000968,
> + HWVfDmaFec4GulRespPtrHiRegVf = 0x0000096C,
> + HWVfDmaFec4GdlDescBaseLoRegVf = 0x00000980,
> + HWVfDmaFec4GdlDescBaseHiRegVf = 0x00000984,
> + HWVfDmaFec4GdlRespPtrLoRegVf = 0x00000988,
> + HWVfDmaFec4GdlRespPtrHiRegVf = 0x0000098C,
> + HWVfDmaFftDescBaseLoRegVf = 0x000009A0,
> + HWVfDmaFftDescBaseHiRegVf = 0x000009A4,
> + HWVfDmaFftRespPtrLoRegVf = 0x000009A8,
> + HWVfDmaFftRespPtrHiRegVf = 0x000009AC,
> + HWVfQmgrAqResetVf = 0x00000E00,
> + HWVfQmgrRingSizeVf = 0x00000E04,
> + HWVfQmgrGrpDepthLog20Vf = 0x00000E08,
> + HWVfQmgrGrpDepthLog21Vf = 0x00000E0C,
> + HWVfQmgrGrpFunction0Vf = 0x00000E10,
> + HWVfQmgrGrpFunction1Vf = 0x00000E14,
> + HWVfPmACntrlRegVf = 0x00000F40,
> + HWVfPmACountVf = 0x00000F48,
> + HWVfPmAKCntLoVf = 0x00000F50,
> + HWVfPmAKCntHiVf = 0x00000F54,
> + HWVfPmADeltaCntLoVf = 0x00000F60,
> + HWVfPmADeltaCntHiVf = 0x00000F64,
> + HWVfPmBCntrlRegVf = 0x00000F80,
> + HWVfPmBCountVf = 0x00000F88,
> + HWVfPmBKCntLoVf = 0x00000F90,
> + HWVfPmBKCntHiVf = 0x00000F94,
> + HWVfPmBDeltaCntLoVf = 0x00000FA0,
> + HWVfPmBDeltaCntHiVf = 0x00000FA4,
> + HWVfPmCCntrlRegVf = 0x00000FC0,
> + HWVfPmCCountVf = 0x00000FC8,
> + HWVfPmCKCntLoVf = 0x00000FD0,
> + HWVfPmCKCntHiVf = 0x00000FD4,
> + HWVfPmCDeltaCntLoVf = 0x00000FE0,
> + HWVfPmCDeltaCntHiVf = 0x00000FE4
> +};
> +
> +/* TIP VF Interrupt numbers */
> +enum {
> + ACC200_VF_INT_QMGR_AQ_OVERFLOW = 0,
> + ACC200_VF_INT_DOORBELL_PF_2_VF = 1,
> + ACC200_VF_INT_ILLEGAL_FORMAT = 2,
> + ACC200_VF_INT_QMGR_DISABLED_ACCESS = 3,
> + ACC200_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
> + ACC200_VF_INT_DMA_DL_DESC_IRQ = 5,
> + ACC200_VF_INT_DMA_UL_DESC_IRQ = 6,
> + ACC200_VF_INT_DMA_FFT_DESC_IRQ = 7,
> + ACC200_VF_INT_DMA_UL5G_DESC_IRQ = 8,
> + ACC200_VF_INT_DMA_DL5G_DESC_IRQ = 9,
> + ACC200_VF_INT_DMA_MLD_DESC_IRQ = 10,
> +};
> +
> +#endif /* ACC200_VF_ENUM_H */
> diff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c
> index db8b641..5554488 100644
> --- a/drivers/baseband/acc/rte_acc200_pmd.c
> +++ b/drivers/baseband/acc/rte_acc200_pmd.c
> @@ -34,6 +34,8 @@
> acc200_dev_close(struct rte_bbdev *dev)
> {
> RTE_SET_USED(dev);
> + /* Ensure all in flight HW transactions are completed */
> + usleep(ACC_LONG_WAIT);
> return 0;
> }
>
Above change is unrelated to the purpose of this patch.
With the acc200_dev_close() change moved to patch 4:
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Thanks,
Maxime
new file mode 100644
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#ifndef ACC200_PF_ENUM_H
+#define ACC200_PF_ENUM_H
+
+/*
+ * ACC200 Register mapping on PF BAR0
+ * This is automatically generated from RDL, format may change with new RDL
+ * Release.
+ * Variable names are as is
+ */
+enum {
+ HWPfQmgrEgressQueuesTemplate = 0x0007FC00,
+ HWPfQmgrIngressAq = 0x00080000,
+ HWPfQmgrDepthLog2Grp = 0x00A00200,
+ HWPfQmgrTholdGrp = 0x00A00300,
+ HWPfQmgrGrpTmplateReg0Indx = 0x00A00600,
+ HWPfQmgrGrpTmplateReg1Indx = 0x00A00700,
+ HWPfQmgrGrpTmplateReg2indx = 0x00A00800,
+ HWPfQmgrGrpTmplateReg3Indx = 0x00A00900,
+ HWPfQmgrGrpTmplateReg4Indx = 0x00A00A00,
+ HWPfQmgrVfBaseAddr = 0x00A01000,
+ HWPfQmgrArbQDepthGrp = 0x00A02F00,
+ HWPfQmgrGrpFunction0 = 0x00A02F40,
+ HWPfQmgrGrpFunction1 = 0x00A02F44,
+ HWPfQmgrGrpPriority = 0x00A02F48,
+ HWPfQmgrAqEnableVf = 0x00A10000,
+ HWPfQmgrRingSizeVf = 0x00A20004,
+ HWPfQmgrGrpDepthLog20Vf = 0x00A20008,
+ HWPfQmgrGrpDepthLog21Vf = 0x00A2000C,
+ HWPfFabricM2iBufferReg = 0x00B30000,
+ HWPfFabricI2Mdma_weight = 0x00B31044,
+ HwPfFecUl5gIbDebugReg = 0x00B40200,
+ HWPfFftConfig0 = 0x00B58004,
+ HWPfFftRamPageAccess = 0x00B5800C,
+ HWPfFftRamOff = 0x00B58800,
+ HWPfDmaConfig0Reg = 0x00B80000,
+ HWPfDmaConfig1Reg = 0x00B80004,
+ HWPfDmaQmgrAddrReg = 0x00B80008,
+ HWPfDmaAxcacheReg = 0x00B80010,
+ HWPfDmaAxiControl = 0x00B8002C,
+ HWPfDmaQmanen = 0x00B80040,
+ HWPfDma4gdlIbThld = 0x00B800CC,
+ HWPfDmaCfgRrespBresp = 0x00B80814,
+ HWPfDmaDescriptorSignatuture = 0x00B80868,
+ HWPfDmaErrorDetectionEn = 0x00B80870,
+ HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020,
+ HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024,
+ HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028,
+ HWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C,
+ HWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040,
+ HWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044,
+ HWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048,
+ HWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C,
+ HWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060,
+ HWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064,
+ HWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068,
+ HWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C,
+ HWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080,
+ HWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084,
+ HWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088,
+ HWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C,
+ HWPDmaFftDescBaseLoRegVf = 0x00B880A0,
+ HWPDmaFftDescBaseHiRegVf = 0x00B880A4,
+ HWPDmaFftRespPtrLoRegVf = 0x00B880A8,
+ HWPDmaFftRespPtrHiRegVf = 0x00B880AC,
+ HWPfQosmonAEvalOverflow0 = 0x00B90008,
+ HWPfPermonACntrlRegVf = 0x00B98000,
+ HWPfQosmonBEvalOverflow0 = 0x00BA0008,
+ HWPfPermonBCntrlRegVf = 0x00BA8000,
+ HWPfPermonCCntrlRegVf = 0x00BB8000,
+ HWPfHiInfoRingBaseLoRegPf = 0x00C84014,
+ HWPfHiInfoRingBaseHiRegPf = 0x00C84018,
+ HWPfHiInfoRingPointerRegPf = 0x00C8401C,
+ HWPfHiInfoRingIntWrEnRegPf = 0x00C84020,
+ HWPfHiBlockTransmitOnErrorEn = 0x00C84038,
+ HWPfHiCfgMsiIntWrEnRegPf = 0x00C84040,
+ HWPfHiMsixVectorMapperPf = 0x00C84060,
+ HWPfHiPfMode = 0x00C84108,
+ HWPfHiClkGateHystReg = 0x00C8410C,
+ HWPfHiMsiDropEnableReg = 0x00C84114,
+ HWPfHiSectionPowerGatingReq = 0x00C84128,
+ HWPfHiSectionPowerGatingAck = 0x00C8412C,
+};
+
+/* TIP PF Interrupt numbers */
+enum {
+ ACC200_PF_INT_QMGR_AQ_OVERFLOW = 0,
+ ACC200_PF_INT_DOORBELL_VF_2_PF = 1,
+ ACC200_PF_INT_ILLEGAL_FORMAT = 2,
+ ACC200_PF_INT_QMGR_DISABLED_ACCESS = 3,
+ ACC200_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
+ ACC200_PF_INT_DMA_DL_DESC_IRQ = 5,
+ ACC200_PF_INT_DMA_UL_DESC_IRQ = 6,
+ ACC200_PF_INT_DMA_FFT_DESC_IRQ = 7,
+ ACC200_PF_INT_DMA_UL5G_DESC_IRQ = 8,
+ ACC200_PF_INT_DMA_DL5G_DESC_IRQ = 9,
+ ACC200_PF_INT_DMA_MLD_DESC_IRQ = 10,
+ ACC200_PF_INT_ARAM_ECC_1BIT_ERR = 11,
+ ACC200_PF_INT_PARITY_ERR = 12,
+ ACC200_PF_INT_QMGR_ERR = 13,
+ ACC200_PF_INT_INT_REQ_OVERFLOW = 14,
+ ACC200_PF_INT_APB_TIMEOUT = 15,
+};
+
+#endif /* ACC200_PF_ENUM_H */
@@ -6,6 +6,8 @@
#define _RTE_ACC200_PMD_H_
#include "acc_common.h"
+#include "acc200_pf_enum.h"
+#include "acc200_vf_enum.h"
/* Helper macro for logging */
#define rte_bbdev_log(level, fmt, ...) \
@@ -29,4 +31,165 @@
#define RTE_ACC200_PF_DEVICE_ID (0x57C0)
#define RTE_ACC200_VF_DEVICE_ID (0x57C1)
+#define ACC200_MAX_PF_MSIX (256+32)
+#define ACC200_MAX_VF_MSIX (256+7)
+
+/* Values used in writing to the registers */
+#define ACC200_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
+
+/* Number of Virtual Functions ACC200 supports */
+#define ACC200_NUM_VFS 16
+#define ACC200_NUM_QGRPS 16
+#define ACC200_NUM_AQS 16
+
+#define ACC200_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
+#define ACC200_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
+#define ACC200_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)
+
+/* Mapping of signals for the available engines */
+#define ACC200_SIG_UL_5G 0
+#define ACC200_SIG_UL_5G_LAST 4
+#define ACC200_SIG_DL_5G 10
+#define ACC200_SIG_DL_5G_LAST 11
+#define ACC200_SIG_UL_4G 12
+#define ACC200_SIG_UL_4G_LAST 16
+#define ACC200_SIG_DL_4G 21
+#define ACC200_SIG_DL_4G_LAST 23
+#define ACC200_SIG_FFT 24
+#define ACC200_SIG_FFT_LAST 24
+
+#define ACC200_NUM_ACCS 5 /* FIXMEFFT */
+
+/* ACC200 Configuration */
+#define ACC200_FABRIC_MODE 0x8000103
+#define ACC200_CFG_DMA_ERROR 0x3DF
+#define ACC200_CFG_AXI_CACHE 0x11
+#define ACC200_CFG_QMGR_HI_P 0x0F0F
+#define ACC200_RESET_HARD 0x1FF
+#define ACC200_ENGINES_MAX 9
+#define ACC200_GPEX_AXIMAP_NUM 17
+#define ACC200_CLOCK_GATING_EN 0x30000
+#define ACC200_FFT_CFG_0 0x2001
+#define ACC200_FFT_RAM_EN 0x80008000
+#define ACC200_FFT_RAM_DIS 0x0
+#define ACC200_FFT_RAM_SIZE 512
+#define ACC200_CLK_EN 0x00010A01
+#define ACC200_CLK_DIS 0x01F10A01
+#define ACC200_PG_MASK_0 0x1F
+#define ACC200_PG_MASK_1 0xF
+#define ACC200_PG_MASK_2 0x1
+#define ACC200_PG_MASK_3 0x0
+#define ACC200_PG_MASK_FFT 1
+#define ACC200_PG_MASK_4GUL 4
+#define ACC200_PG_MASK_5GUL 8
+#define ACC200_STATUS_WAIT 10
+#define ACC200_STATUS_TO 100
+
+struct acc200_registry_addr {
+ unsigned int dma_ring_dl5g_hi;
+ unsigned int dma_ring_dl5g_lo;
+ unsigned int dma_ring_ul5g_hi;
+ unsigned int dma_ring_ul5g_lo;
+ unsigned int dma_ring_dl4g_hi;
+ unsigned int dma_ring_dl4g_lo;
+ unsigned int dma_ring_ul4g_hi;
+ unsigned int dma_ring_ul4g_lo;
+ unsigned int dma_ring_fft_hi;
+ unsigned int dma_ring_fft_lo;
+ unsigned int ring_size;
+ unsigned int info_ring_hi;
+ unsigned int info_ring_lo;
+ unsigned int info_ring_en;
+ unsigned int info_ring_ptr;
+ unsigned int tail_ptrs_dl5g_hi;
+ unsigned int tail_ptrs_dl5g_lo;
+ unsigned int tail_ptrs_ul5g_hi;
+ unsigned int tail_ptrs_ul5g_lo;
+ unsigned int tail_ptrs_dl4g_hi;
+ unsigned int tail_ptrs_dl4g_lo;
+ unsigned int tail_ptrs_ul4g_hi;
+ unsigned int tail_ptrs_ul4g_lo;
+ unsigned int tail_ptrs_fft_hi;
+ unsigned int tail_ptrs_fft_lo;
+ unsigned int depth_log0_offset;
+ unsigned int depth_log1_offset;
+ unsigned int qman_group_func;
+ unsigned int hi_mode;
+ unsigned int pmon_ctrl_a;
+ unsigned int pmon_ctrl_b;
+ unsigned int pmon_ctrl_c;
+};
+
+/* Structure holding registry addresses for PF */
+static const struct acc200_registry_addr pf_reg_addr = {
+ .dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
+ .dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
+ .dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
+ .dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
+ .dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
+ .dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
+ .dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
+ .dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
+ .dma_ring_fft_hi = HWPDmaFftDescBaseHiRegVf,
+ .dma_ring_fft_lo = HWPDmaFftDescBaseLoRegVf,
+ .ring_size = HWPfQmgrRingSizeVf,
+ .info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
+ .info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
+ .info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
+ .info_ring_ptr = HWPfHiInfoRingPointerRegPf,
+ .tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
+ .tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
+ .tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
+ .tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
+ .tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
+ .tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
+ .tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
+ .tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
+ .tail_ptrs_fft_hi = HWPDmaFftRespPtrHiRegVf,
+ .tail_ptrs_fft_lo = HWPDmaFftRespPtrLoRegVf,
+ .depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
+ .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
+ .qman_group_func = HWPfQmgrGrpFunction0,
+ .hi_mode = HWPfHiMsixVectorMapperPf,
+ .pmon_ctrl_a = HWPfPermonACntrlRegVf,
+ .pmon_ctrl_b = HWPfPermonBCntrlRegVf,
+ .pmon_ctrl_c = HWPfPermonCCntrlRegVf,
+};
+
+/* Structure holding registry addresses for VF */
+static const struct acc200_registry_addr vf_reg_addr = {
+ .dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
+ .dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
+ .dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
+ .dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
+ .dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
+ .dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
+ .dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
+ .dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
+ .dma_ring_fft_hi = HWVfDmaFftDescBaseHiRegVf,
+ .dma_ring_fft_lo = HWVfDmaFftDescBaseLoRegVf,
+ .ring_size = HWVfQmgrRingSizeVf,
+ .info_ring_hi = HWVfHiInfoRingBaseHiVf,
+ .info_ring_lo = HWVfHiInfoRingBaseLoVf,
+ .info_ring_en = HWVfHiInfoRingIntWrEnVf,
+ .info_ring_ptr = HWVfHiInfoRingPointerVf,
+ .tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
+ .tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
+ .tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
+ .tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
+ .tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
+ .tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
+ .tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
+ .tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
+ .tail_ptrs_fft_hi = HWVfDmaFftRespPtrHiRegVf,
+ .tail_ptrs_fft_lo = HWVfDmaFftRespPtrLoRegVf,
+ .depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
+ .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
+ .qman_group_func = HWVfQmgrGrpFunction0Vf,
+ .hi_mode = HWVfHiMsixVectorMapperVf,
+ .pmon_ctrl_a = HWVfPmACntrlRegVf,
+ .pmon_ctrl_b = HWVfPmBCntrlRegVf,
+ .pmon_ctrl_c = HWVfPmCCntrlRegVf,
+};
+
#endif /* _RTE_ACC200_PMD_H_ */
new file mode 100644
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#ifndef ACC200_VF_ENUM_H
+#define ACC200_VF_ENUM_H
+
+/*
+ * ACC200 Register mapping on VF BAR0
+ * This is automatically generated from RDL, format may change with new RDL
+ */
+enum {
+ HWVfQmgrIngressAq = 0x00000000,
+ HWVfHiVfToPfDbellVf = 0x00000800,
+ HWVfHiPfToVfDbellVf = 0x00000808,
+ HWVfHiInfoRingBaseLoVf = 0x00000810,
+ HWVfHiInfoRingBaseHiVf = 0x00000814,
+ HWVfHiInfoRingPointerVf = 0x00000818,
+ HWVfHiInfoRingIntWrEnVf = 0x00000820,
+ HWVfHiInfoRingPf2VfWrEnVf = 0x00000824,
+ HWVfHiMsixVectorMapperVf = 0x00000860,
+ HWVfDmaFec5GulDescBaseLoRegVf = 0x00000920,
+ HWVfDmaFec5GulDescBaseHiRegVf = 0x00000924,
+ HWVfDmaFec5GulRespPtrLoRegVf = 0x00000928,
+ HWVfDmaFec5GulRespPtrHiRegVf = 0x0000092C,
+ HWVfDmaFec5GdlDescBaseLoRegVf = 0x00000940,
+ HWVfDmaFec5GdlDescBaseHiRegVf = 0x00000944,
+ HWVfDmaFec5GdlRespPtrLoRegVf = 0x00000948,
+ HWVfDmaFec5GdlRespPtrHiRegVf = 0x0000094C,
+ HWVfDmaFec4GulDescBaseLoRegVf = 0x00000960,
+ HWVfDmaFec4GulDescBaseHiRegVf = 0x00000964,
+ HWVfDmaFec4GulRespPtrLoRegVf = 0x00000968,
+ HWVfDmaFec4GulRespPtrHiRegVf = 0x0000096C,
+ HWVfDmaFec4GdlDescBaseLoRegVf = 0x00000980,
+ HWVfDmaFec4GdlDescBaseHiRegVf = 0x00000984,
+ HWVfDmaFec4GdlRespPtrLoRegVf = 0x00000988,
+ HWVfDmaFec4GdlRespPtrHiRegVf = 0x0000098C,
+ HWVfDmaFftDescBaseLoRegVf = 0x000009A0,
+ HWVfDmaFftDescBaseHiRegVf = 0x000009A4,
+ HWVfDmaFftRespPtrLoRegVf = 0x000009A8,
+ HWVfDmaFftRespPtrHiRegVf = 0x000009AC,
+ HWVfQmgrAqResetVf = 0x00000E00,
+ HWVfQmgrRingSizeVf = 0x00000E04,
+ HWVfQmgrGrpDepthLog20Vf = 0x00000E08,
+ HWVfQmgrGrpDepthLog21Vf = 0x00000E0C,
+ HWVfQmgrGrpFunction0Vf = 0x00000E10,
+ HWVfQmgrGrpFunction1Vf = 0x00000E14,
+ HWVfPmACntrlRegVf = 0x00000F40,
+ HWVfPmACountVf = 0x00000F48,
+ HWVfPmAKCntLoVf = 0x00000F50,
+ HWVfPmAKCntHiVf = 0x00000F54,
+ HWVfPmADeltaCntLoVf = 0x00000F60,
+ HWVfPmADeltaCntHiVf = 0x00000F64,
+ HWVfPmBCntrlRegVf = 0x00000F80,
+ HWVfPmBCountVf = 0x00000F88,
+ HWVfPmBKCntLoVf = 0x00000F90,
+ HWVfPmBKCntHiVf = 0x00000F94,
+ HWVfPmBDeltaCntLoVf = 0x00000FA0,
+ HWVfPmBDeltaCntHiVf = 0x00000FA4,
+ HWVfPmCCntrlRegVf = 0x00000FC0,
+ HWVfPmCCountVf = 0x00000FC8,
+ HWVfPmCKCntLoVf = 0x00000FD0,
+ HWVfPmCKCntHiVf = 0x00000FD4,
+ HWVfPmCDeltaCntLoVf = 0x00000FE0,
+ HWVfPmCDeltaCntHiVf = 0x00000FE4
+};
+
+/* TIP VF Interrupt numbers */
+enum {
+ ACC200_VF_INT_QMGR_AQ_OVERFLOW = 0,
+ ACC200_VF_INT_DOORBELL_PF_2_VF = 1,
+ ACC200_VF_INT_ILLEGAL_FORMAT = 2,
+ ACC200_VF_INT_QMGR_DISABLED_ACCESS = 3,
+ ACC200_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
+ ACC200_VF_INT_DMA_DL_DESC_IRQ = 5,
+ ACC200_VF_INT_DMA_UL_DESC_IRQ = 6,
+ ACC200_VF_INT_DMA_FFT_DESC_IRQ = 7,
+ ACC200_VF_INT_DMA_UL5G_DESC_IRQ = 8,
+ ACC200_VF_INT_DMA_DL5G_DESC_IRQ = 9,
+ ACC200_VF_INT_DMA_MLD_DESC_IRQ = 10,
+};
+
+#endif /* ACC200_VF_ENUM_H */
@@ -34,6 +34,8 @@
acc200_dev_close(struct rte_bbdev *dev)
{
RTE_SET_USED(dev);
+ /* Ensure all in flight HW transactions are completed */
+ usleep(ACC_LONG_WAIT);
return 0;
}