From patchwork Thu Sep 22 00:27:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 116608 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D988A0540; Thu, 22 Sep 2022 02:29:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 08CDD42B9F; Thu, 22 Sep 2022 02:28:27 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 104744282F for ; Thu, 22 Sep 2022 02:28:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663806497; x=1695342497; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=BQ2wuF4qw1B29W7H/4oasA0uYD9Ey6c71wzCakNhWJ0=; b=if7VV2Kzi7F3szV//sE76BYnnyfW6JMF5In1MFAeEURnzxm2qJvofpot hFfVIbFnLxv1unwpTQZd1Owb+S3zvvZ3E2Fu3OpzUfw/y4KGswvA7Hwi0 8LCs3BF/mS49gGz1/HqobKXUtCwp0MxEAyex/FJ1NEmenMbFxDSYchlku siWaFfLn20zp4Ar5jgYveT+hhZ33oSbBm7q6P3yGDtvN67ZJHynXNDjYR 9JFOV7OoERdSDPWMDx1Z7C7Wp3obOamXHUoPYMRyjSe/yRWT6CYn9l4Ex Jh27xytUJ9ZbeK7LOYxpo7GS9is2f0oePaTYpdqd96NNJnGUwL9R0xgxD w==; X-IronPort-AV: E=McAfee;i="6500,9779,10477"; a="279883417" X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="279883417" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 17:28:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="615010989" Received: from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245]) by orsmga007.jf.intel.com with ESMTP; 21 Sep 2022 17:28:15 -0700 From: Nic Chautru To: dev@dpdk.org, thomas@monjalon.net Cc: maxime.coquelin@redhat.com, trix@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com, hemant.agrawal@nxp.com, david.marchand@redhat.com, stephen@networkplumber.org, hernan.vargas@intel.com, Nic Chautru Subject: [PATCH v4 12/14] baseband/acc: add device status and vf2pf comms Date: Wed, 21 Sep 2022 17:27:38 -0700 Message-Id: <1663806460-45162-13-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1663806460-45162-1-git-send-email-nicolas.chautru@intel.com> References: <1663806460-45162-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to expose the device status seen from the host through v2pf mailbox communication. Signed-off-by: Nic Chautru Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc200_pmd.c | 61 +++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 17 deletions(-) diff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c index b8b621a..3c2931b 100644 --- a/drivers/baseband/acc/rte_acc200_pmd.c +++ b/drivers/baseband/acc/rte_acc200_pmd.c @@ -201,23 +201,47 @@ rte_bbdev_log_debug( "%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u %u AQ %u %u %u %u %u Len %u %u %u %u %u\n", (d->pf_device) ? "PF" : "VF", - (acc_conf->input_pos_llr_1_bit) ? "POS" : "NEG", - (acc_conf->output_pos_llr_1_bit) ? "POS" : "NEG", - acc_conf->q_ul_4g.num_qgroups, - acc_conf->q_dl_4g.num_qgroups, - acc_conf->q_ul_5g.num_qgroups, - acc_conf->q_dl_5g.num_qgroups, - acc_conf->q_fft.num_qgroups, - acc_conf->q_ul_4g.num_aqs_per_groups, - acc_conf->q_dl_4g.num_aqs_per_groups, - acc_conf->q_ul_5g.num_aqs_per_groups, - acc_conf->q_dl_5g.num_aqs_per_groups, - acc_conf->q_fft.num_aqs_per_groups, - acc_conf->q_ul_4g.aq_depth_log2, - acc_conf->q_dl_4g.aq_depth_log2, - acc_conf->q_ul_5g.aq_depth_log2, - acc_conf->q_dl_5g.aq_depth_log2, - acc_conf->q_fft.aq_depth_log2); + (acc200_conf->input_pos_llr_1_bit) ? "POS" : "NEG", + (acc200_conf->output_pos_llr_1_bit) ? "POS" : "NEG", + acc200_conf->q_ul_4g.num_qgroups, + acc200_conf->q_dl_4g.num_qgroups, + acc200_conf->q_ul_5g.num_qgroups, + acc200_conf->q_dl_5g.num_qgroups, + acc200_conf->q_fft.num_qgroups, + acc200_conf->q_ul_4g.num_aqs_per_groups, + acc200_conf->q_dl_4g.num_aqs_per_groups, + acc200_conf->q_ul_5g.num_aqs_per_groups, + acc200_conf->q_dl_5g.num_aqs_per_groups, + acc200_conf->q_fft.num_aqs_per_groups, + acc200_conf->q_ul_4g.aq_depth_log2, + acc200_conf->q_dl_4g.aq_depth_log2, + acc200_conf->q_ul_5g.aq_depth_log2, + acc200_conf->q_dl_5g.aq_depth_log2, + acc200_conf->q_fft.aq_depth_log2); +} + +static inline void +acc200_vf2pf(struct acc_device *d, unsigned int payload) +{ + acc_reg_write(d, HWVfHiVfToPfDbellVf, payload); +} + +/* Request device status information */ +static inline uint32_t +acc200_device_status(struct rte_bbdev *dev) +{ + struct acc_device *d = dev->data->dev_private; + uint32_t reg, time_out = 0; + if (d->pf_device) + return RTE_BBDEV_DEV_NOT_SUPPORTED; + acc200_vf2pf(d, ACC_VF2PF_STATUS_REQUEST); + reg = acc_reg_read(d, HWVfHiPfToVfDbellVf); + while ((time_out < ACC200_STATUS_TO) && (reg == RTE_BBDEV_DEV_NOSTATUS)) { + usleep(ACC200_STATUS_WAIT); /*< Wait or VF->PF->VF Comms */ + reg = acc_reg_read(d, HWVfHiPfToVfDbellVf); + time_out++; + } + return reg; } /* Checks PF Info Ring to find the interrupt cause and handles it accordingly */ @@ -537,6 +561,7 @@ /* Mark as configured properly */ d->configured = true; + acc200_vf2pf(d, ACC_VF2PF_USING_VF); rte_bbdev_log_debug( "ACC200 (%s) configured sw_rings = %p, sw_rings_iova = %#" @@ -1047,6 +1072,8 @@ /* Read and save the populated config from ACC200 registers */ fetch_acc200_config(dev); + /* Check the status of device */ + dev_info->device_status = acc200_device_status(dev); /* Exposed number of queues */ dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0;