From patchwork Sat Sep 18 14:31:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99288 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DF36AA0C45; Sat, 18 Sep 2021 16:32:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 697F7410F7; Sat, 18 Sep 2021 16:32:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E7E38410EF for ; Sat, 18 Sep 2021 16:32:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18IDnd02010787 for ; Sat, 18 Sep 2021 07:32:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=EbkKlXRxuqJnc32rEeYtlivPPgsx4+ET29QgKXF1/9g=; b=IPK7i7ywkQ0GPvMZXsLdhRakT1i9y6eO6VblInFcAWQHFnQwPyXmj8ve1vhIIZMbpzzU 0l1oCNWLgyXvV+S6gUUv/doax2rSWjRRjoNnDJ63lwCAKhgmSSM+33+xoMX0sqLqpJJg fLi1DDklNjcKnXZUBtMuoMN6Z/BFsc/3pWYq6OgFAj5BUYPwy/95maEdwEzMIdq6WMLb oQ98FE6FlUhM/zJc176E3uNdN2+7D4Zj7hf81BlGE6EQlDnJ//sEJMWDkfKxu0kHW5Ob UT9h/PW5lCk3MWfpArgLVInP6q3lmE4KuKVM3L0Oh5fRG8JE3rPAD7jFG1/HJPnCVS+I Rw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3b5fmm08yy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 18 Sep 2021 07:32:20 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 18 Sep 2021 07:32:17 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:17 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id 8FFF13F705E; Sat, 18 Sep 2021 07:32:16 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Sat, 18 Sep 2021 10:31:53 -0400 Message-ID: <1631975519-30924-4-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NGdukiRHNlBdI5CevzQXMVe-gkklszr8 X-Proofpoint-GUID: NGdukiRHNlBdI5CevzQXMVe-gkklszr8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 3/8] common/cnxk: increase sched weight and shaper burst limit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nithin Dabilpuram Increase sched weight and shaper burst limit for cn10k. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/hw/nix.h | 13 +++++++---- drivers/common/cnxk/roc_nix.h | 23 ++++++++++++++++++- drivers/common/cnxk/roc_nix_priv.h | 11 ++++++---- drivers/common/cnxk/roc_nix_tm.c | 2 +- drivers/common/cnxk/roc_nix_tm_ops.c | 10 +++++---- drivers/common/cnxk/roc_nix_tm_utils.c | 40 +++++++++++++++++++++++++--------- 6 files changed, 75 insertions(+), 24 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index bc908c2..d205438 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2134,8 +2134,9 @@ struct nix_lso_format { 0) /* NIX burst limits */ -#define NIX_TM_MAX_BURST_EXPONENT 0xf -#define NIX_TM_MAX_BURST_MANTISSA 0xff +#define NIX_TM_MAX_BURST_EXPONENT 0xful +#define NIX_TM_MAX_BURST_MANTISSA 0x7ffful +#define NIX_CN9K_TM_MAX_BURST_MANTISSA 0xfful /* NIX burst calculation * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA]) @@ -2147,7 +2148,7 @@ struct nix_lso_format { * / 256 */ #define NIX_TM_SHAPER_BURST(exponent, mantissa) \ - (((256 + (mantissa)) << ((exponent) + 1)) / 256) + (((256ul + (mantissa)) << ((exponent) + 1)) / 256ul) /* Burst limit in Bytes */ #define NIX_TM_MIN_SHAPER_BURST NIX_TM_SHAPER_BURST(0, 0) @@ -2156,13 +2157,17 @@ struct nix_lso_format { NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT, \ NIX_TM_MAX_BURST_MANTISSA) +#define NIX_CN9K_TM_MAX_SHAPER_BURST \ + NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT, \ + NIX_CN9K_TM_MAX_BURST_MANTISSA) + /* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */ #define NIX_TM_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1) #define NIX_TM_LENGTH_ADJUST_MAX 255 #define NIX_TM_TLX_SP_PRIO_MAX 10 #define NIX_CN9K_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1) -#define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(14) - 1) +#define NIX_TM_RR_WEIGHT_MAX (BIT_ULL(14) - 1) /* [CN9K, CN10K) */ #define NIX_CN9K_TXSCH_LVL_SMQ_MAX 512 diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index ac7bd7e..90dc413 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -277,6 +277,28 @@ enum roc_nix_lso_tun_type { ROC_NIX_LSO_TUN_MAX, }; +/* Restrict CN9K sched weight to have a minimum quantum */ +#define ROC_NIX_CN9K_TM_RR_WEIGHT_MAX 255u + +/* NIX TM Inlines */ +static inline uint64_t +roc_nix_tm_max_sched_wt_get(void) +{ + if (roc_model_is_cn9k()) + return ROC_NIX_CN9K_TM_RR_WEIGHT_MAX; + else + return NIX_TM_RR_WEIGHT_MAX; +} + +static inline uint64_t +roc_nix_tm_max_shaper_burst_get(void) +{ + if (roc_model_is_cn9k()) + return NIX_CN9K_TM_MAX_SHAPER_BURST; + else + return NIX_TM_MAX_SHAPER_BURST; +} + /* Dev */ int __roc_api roc_nix_dev_init(struct roc_nix *roc_nix); int __roc_api roc_nix_dev_fini(struct roc_nix *roc_nix); @@ -324,7 +346,6 @@ void __roc_api roc_nix_rx_queue_intr_disable(struct roc_nix *roc_nix, void __roc_api roc_nix_unregister_cq_irqs(struct roc_nix *roc_nix); /* Traffic Management */ -#define ROC_NIX_TM_MAX_SCHED_WT ((uint8_t)~0) #define ROC_NIX_TM_SHAPER_PROFILE_NONE UINT32_MAX #define ROC_NIX_TM_NODE_ID_INVALID UINT32_MAX diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 9dc0c88..cc8e822 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -256,11 +256,14 @@ struct nix_tm_shaper_data { static inline uint64_t nix_tm_weight_to_rr_quantum(uint64_t weight) { - uint64_t max = (roc_model_is_cn9k() ? NIX_CN9K_TM_RR_QUANTUM_MAX : - NIX_TM_RR_QUANTUM_MAX); + uint64_t max = NIX_CN9K_TM_RR_QUANTUM_MAX; - weight &= (uint64_t)ROC_NIX_TM_MAX_SCHED_WT; - return (weight * max) / ROC_NIX_TM_MAX_SCHED_WT; + /* From CN10K onwards, we only configure RR weight */ + if (!roc_model_is_cn9k()) + return weight; + + weight &= (uint64_t)max; + return (weight * max) / ROC_NIX_CN9K_TM_RR_WEIGHT_MAX; } static inline bool diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index ad54e17..947320a 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -223,7 +223,7 @@ if (rc) return rc; - if (node->weight > ROC_NIX_TM_MAX_SCHED_WT) + if (node->weight > roc_nix_tm_max_sched_wt_get()) return NIX_ERR_TM_WEIGHT_EXCEED; /* Maintain minimum weight */ diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index d9741f5..a313023 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -83,6 +83,7 @@ { struct nix *nix = roc_nix_to_nix_priv(roc_nix); uint64_t commit_rate, commit_sz; + uint64_t min_burst, max_burst; uint64_t peak_rate, peak_sz; uint32_t id; @@ -92,6 +93,9 @@ peak_rate = profile->peak.rate; peak_sz = profile->peak.size; + min_burst = NIX_TM_MIN_SHAPER_BURST; + max_burst = roc_nix_tm_max_shaper_burst_get(); + if (nix_tm_shaper_profile_search(nix, id) && !skip_ins) return NIX_ERR_TM_SHAPER_PROFILE_EXISTS; @@ -105,8 +109,7 @@ /* commit rate and burst size can be enabled/disabled */ if (commit_rate || commit_sz) { - if (commit_sz < NIX_TM_MIN_SHAPER_BURST || - commit_sz > NIX_TM_MAX_SHAPER_BURST) + if (commit_sz < min_burst || commit_sz > max_burst) return NIX_ERR_TM_INVALID_COMMIT_SZ; else if (!nix_tm_shaper_rate_conv(commit_rate, NULL, NULL, NULL)) @@ -115,8 +118,7 @@ /* Peak rate and burst size can be enabled/disabled */ if (peak_sz || peak_rate) { - if (peak_sz < NIX_TM_MIN_SHAPER_BURST || - peak_sz > NIX_TM_MAX_SHAPER_BURST) + if (peak_sz < min_burst || peak_sz > max_burst) return NIX_ERR_TM_INVALID_PEAK_SZ; else if (!nix_tm_shaper_rate_conv(peak_rate, NULL, NULL, NULL)) return NIX_ERR_TM_INVALID_PEAK_RATE; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 6b9543e..00604b1 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -8,9 +8,23 @@ static inline uint64_t nix_tm_shaper2regval(struct nix_tm_shaper_data *shaper) { - return (shaper->burst_exponent << 37) | (shaper->burst_mantissa << 29) | - (shaper->div_exp << 13) | (shaper->exponent << 9) | - (shaper->mantissa << 1); + uint64_t regval; + + if (roc_model_is_cn9k()) { + regval = (shaper->burst_exponent << 37); + regval |= (shaper->burst_mantissa << 29); + regval |= (shaper->div_exp << 13); + regval |= (shaper->exponent << 9); + regval |= (shaper->mantissa << 1); + return regval; + } + + regval = (shaper->burst_exponent << 44); + regval |= (shaper->burst_mantissa << 29); + regval |= (shaper->div_exp << 13); + regval |= (shaper->exponent << 9); + regval |= (shaper->mantissa << 1); + return regval; } uint16_t @@ -178,20 +192,26 @@ struct nix_tm_node * nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p) { + uint64_t min_burst, max_burst; uint64_t exponent, mantissa; + uint32_t max_mantissa; + + min_burst = NIX_TM_MIN_SHAPER_BURST; + max_burst = roc_nix_tm_max_shaper_burst_get(); - if (value < NIX_TM_MIN_SHAPER_BURST || value > NIX_TM_MAX_SHAPER_BURST) + if (value < min_burst || value > max_burst) return 0; + max_mantissa = (roc_model_is_cn9k() ? NIX_CN9K_TM_MAX_BURST_MANTISSA : + NIX_TM_MAX_BURST_MANTISSA); /* Calculate burst exponent and mantissa using * the following formula: * - * value = (((256 + mantissa) << (exponent + 1) - / 256) + * value = (((256 + mantissa) << (exponent + 1) / 256) * */ exponent = NIX_TM_MAX_BURST_EXPONENT; - mantissa = NIX_TM_MAX_BURST_MANTISSA; + mantissa = max_mantissa; while (value < (1ull << (exponent + 1))) exponent -= 1; @@ -199,8 +219,7 @@ struct nix_tm_node * while (value < ((256 + mantissa) << (exponent + 1)) / 256) mantissa -= 1; - if (exponent > NIX_TM_MAX_BURST_EXPONENT || - mantissa > NIX_TM_MAX_BURST_MANTISSA) + if (exponent > NIX_TM_MAX_BURST_EXPONENT || mantissa > max_mantissa) return 0; if (exponent_p) @@ -544,6 +563,7 @@ struct nix_tm_node * uint64_t rr_quantum; uint8_t k = 0; + /* For CN9K, weight needs to be converted to quantum */ rr_quantum = nix_tm_weight_to_rr_quantum(node->weight); /* For children to root, strict prio is default if either @@ -554,7 +574,7 @@ struct nix_tm_node * strict_prio = NIX_TM_TL1_DFLT_RR_PRIO; plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, " - "prio 0x%" PRIx64 ", rr_quantum 0x%" PRIx64 " (%p)", + "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)", nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, strict_prio, rr_quantum, node);