From patchwork Mon Sep 6 14:58:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 98084 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7ED66A0C54; Mon, 6 Sep 2021 16:59:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 64F634111F; Mon, 6 Sep 2021 16:59:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id F033C410F8 for ; Mon, 6 Sep 2021 16:59:01 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 186E6M86022984; Mon, 6 Sep 2021 07:59:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=D5UC09JoMxnf5BNcQJF0VxRSkJ+oUHi21vHLA6TlCDo=; b=H9UnIjWbRQn7TSD5VlpCsek3MYIC+UZfhoj7yXbwz/nODafi2sqmaXRDzwxfpHg5e0tw p643SrzQHt7jYhI9MUqd9YWcx3owMXI41ZTuJnLbsXN4TorZCADI0ml3+dxMKuLvAxXh j0wW/Z6XDq+R8ugRcQ2Vf5Jz0389rV0JcNr6eN0X/v2+Rdw7EcwnEqR0HZsH83f5Arp1 P7Rx3/Ykv6/N+EhavXQyziUE7rzGRJZ8Xth/twpCyGUS2NVk3KYUFbpL4vMfSaHXryCK dTZzm/GIsmk7xLj5FTh2ZI8WXRjJDqaNPNqu0Mm56OrE3JChp5YyuaBA4ot2h/wDBxQX ww== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3aw9d2tdgd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 06 Sep 2021 07:59:01 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 6 Sep 2021 07:58:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 6 Sep 2021 07:58:59 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.144]) by maili.marvell.com (Postfix) with ESMTP id 2068B3F709A; Mon, 6 Sep 2021 07:58:53 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Declan Doherty , Fan Zhang , "Konstantin Ananyev" CC: Tejasree Kondoj , Jerin Jacob , Archana Muniganti , Hemant Agrawal , Radu Nicolau , Ciara Power , Gagandeep Singh , , Anoob Joseph Date: Mon, 6 Sep 2021 20:28:26 +0530 Message-ID: <1630940307-78-3-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1630940307-78-1-git-send-email-anoobj@marvell.com> References: <1629093590-115-1-git-send-email-anoobj@marvell.com> <1630940307-78-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: sKn_7UW-0IMbFRtvyRiCa_fpFc4R8vSg X-Proofpoint-ORIG-GUID: sKn_7UW-0IMbFRtvyRiCa_fpFc4R8vSg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-06_06,2021-09-03_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 2/3] crypto/cnxk: add IV in SA in lookaside IPsec debug mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tejasree Kondoj Adding IV in SA in lookaside IPsec debug mode. It helps to verify lookaside PMD using known outbound vectors in lookaside autotest. Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj Acked-by: Akhil Goyal --- drivers/crypto/cnxk/cn10k_ipsec.c | 16 +++++++++ drivers/crypto/cnxk/cn10k_ipsec.h | 2 ++ drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 44 +++++++++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c | 29 +++++++++++++-- drivers/crypto/cnxk/meson.build | 6 ++++ 5 files changed, 95 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c index 5c57cf2..ebb2a7e 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.c +++ b/drivers/crypto/cnxk/cn10k_ipsec.c @@ -57,6 +57,22 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, sa->inst.w7 = ipsec_cpt_inst_w7_get(roc_cpt, sa); +#ifdef LA_IPSEC_DEBUG + /* Use IV from application in debug mode */ + if (ipsec_xfrm->options.iv_gen_disable == 1) { + out_sa->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA; + if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) { + sa->iv_offset = crypto_xfrm->aead.iv.offset; + sa->iv_length = crypto_xfrm->aead.iv.length; + } + } +#else + if (ipsec_xfrm->options.iv_gen_disable != 0) { + plt_err("Application provided IV not supported"); + return -ENOTSUP; + } +#endif + /* Get Rlen calculation data */ ret = cnxk_ipsec_outb_rlens_get(&rlens, ipsec_xfrm, crypto_xfrm); if (ret) diff --git a/drivers/crypto/cnxk/cn10k_ipsec.h b/drivers/crypto/cnxk/cn10k_ipsec.h index bc52c60..6f974b7 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.h +++ b/drivers/crypto/cnxk/cn10k_ipsec.h @@ -21,6 +21,8 @@ struct cn10k_ipsec_sa { /** Pre-populated CPT inst words */ struct cnxk_cpt_inst_tmpl inst; uint16_t max_extended_len; + uint16_t iv_offset; + uint8_t iv_length; }; struct cn10k_sec_session { diff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h index fe91638..862476a 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h +++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h @@ -12,6 +12,41 @@ #include "cn10k_ipsec.h" #include "cnxk_cryptodev.h" +static inline void +ipsec_po_sa_iv_set(struct cn10k_ipsec_sa *sess, struct rte_crypto_op *cop) +{ + uint64_t *iv = &sess->out_sa.iv.u64[0]; + uint64_t *tmp_iv; + + memcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), + 16); + tmp_iv = (uint64_t *)iv; + *tmp_iv = rte_be_to_cpu_64(*tmp_iv); + + tmp_iv = (uint64_t *)(iv + 1); + *tmp_iv = rte_be_to_cpu_64(*tmp_iv); +} + +static inline void +ipsec_po_sa_aes_gcm_iv_set(struct cn10k_ipsec_sa *sess, + struct rte_crypto_op *cop) +{ + uint8_t *iv = &sess->out_sa.iv.s.iv_dbg1[0]; + uint32_t *tmp_iv; + + memcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), + 4); + tmp_iv = (uint32_t *)iv; + *tmp_iv = rte_be_to_cpu_32(*tmp_iv); + + iv = &sess->out_sa.iv.s.iv_dbg2[0]; + memcpy(iv, + rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset + 4), + 4); + tmp_iv = (uint32_t *)iv; + *tmp_iv = rte_be_to_cpu_32(*tmp_iv); +} + static __rte_always_inline int process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess, struct cpt_inst_s *inst) @@ -24,6 +59,15 @@ process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess, return -ENOMEM; } +#ifdef LA_IPSEC_DEBUG + if (sess->out_sa.w2.s.iv_src == ROC_IE_OT_SA_IV_SRC_FROM_SA) { + if (sess->out_sa.w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM) + ipsec_po_sa_aes_gcm_iv_set(sess, cop); + else + ipsec_po_sa_iv_set(sess, cop); + } +#endif + /* Prepare CPT instruction */ inst->w4.u64 = sess->inst.w4; inst->w4.s.dlen = rte_pktmbuf_pkt_len(m_src); diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index c4f7824..4b97639 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -807,7 +807,7 @@ static const struct rte_security_capability sec_caps_templ[] = { .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS, - .options = { 0 } + .options = { 0 }, }, .crypto_capabilities = NULL, }, @@ -818,7 +818,7 @@ static const struct rte_security_capability sec_caps_templ[] = { .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS, - .options = { 0 } + .options = { 0 }, }, .crypto_capabilities = NULL, }, @@ -913,6 +913,24 @@ cnxk_sec_caps_update(struct rte_security_capability *sec_cap) sec_cap->ipsec.options.udp_encap = 1; } +static void +cn10k_sec_caps_update(struct rte_security_capability *sec_cap) +{ + if (sec_cap->ipsec.direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) { +#ifdef LA_IPSEC_DEBUG + sec_cap->ipsec.options.iv_gen_disable = 1; +#endif + } +} + +static void +cn9k_sec_caps_update(struct rte_security_capability *sec_cap) +{ + if (sec_cap->ipsec.direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) { + sec_cap->ipsec.options.iv_gen_disable = 1; + } +} + void cnxk_cpt_caps_populate(struct cnxk_cpt_vf *vf) { @@ -928,6 +946,13 @@ cnxk_cpt_caps_populate(struct cnxk_cpt_vf *vf) vf->sec_caps[i].crypto_capabilities = vf->sec_crypto_caps; cnxk_sec_caps_update(&vf->sec_caps[i]); + + if (roc_model_is_cn10k()) + cn10k_sec_caps_update(&vf->sec_caps[i]); + + if (roc_model_is_cn9k()) + cn9k_sec_caps_update(&vf->sec_caps[i]); + } } diff --git a/drivers/crypto/cnxk/meson.build b/drivers/crypto/cnxk/meson.build index e40d132..437d208 100644 --- a/drivers/crypto/cnxk/meson.build +++ b/drivers/crypto/cnxk/meson.build @@ -24,3 +24,9 @@ sources = files( deps += ['bus_pci', 'common_cnxk', 'security', 'eventdev'] includes += include_directories('../../../lib/net') + +if get_option('buildtype').contains('debug') + cflags += [ '-DLA_IPSEC_DEBUG' ] +else + cflags += [ '-ULA_IPSEC_DEBUG' ] +endif