From patchwork Thu Sep 2 12:22:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 97794 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 21345A0C47; Thu, 2 Sep 2021 14:22:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 08C8D40141; Thu, 2 Sep 2021 14:22:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 847204003E for ; Thu, 2 Sep 2021 14:22:57 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 182817uS011478 for ; Thu, 2 Sep 2021 05:22:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=hlKqhYSmQtfYEyGrO3bZTnx4gqA37zo/tBYNGHvHlSE=; b=a2gXVGhPQLR3ogzag++VPoOCeVOJQ3dIR//14AM5f5iJAn1hHmqi7LzPDW8RFMY1LH3/ fpWSwIeGrx3VMGaKM26xph2e1hY2Ricyf7CvwnmrbhUy3mEq1Xsgyn6Li0ZVYwjqcOYP is2wP35on3Vu4QHA3MRAsP/0ImJkOYMOXnPwKKq62w2ZePEAJHuI7iYsSoqnPTzm/TU4 tAeVaoBTq7okpZL+mKPgYSH5kuR4yoJHIWV3ZyBCkqSsmt+rwlZ5MRvt1hBVNciTTpjM 0T7V3J0V74ZFsikHiHuEzTWIW9ACH+fcoSjO3gtbXdeK41acUcg21VA33VNNETfpkLRH Ig== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3attqmgurb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 02 Sep 2021 05:22:56 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 2 Sep 2021 05:22:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 2 Sep 2021 05:22:54 -0700 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id DA3A43F705E; Thu, 2 Sep 2021 05:22:50 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Vidya Sagar Velumuri , Archana Muniganti , Tejasree Kondoj , , Anoob Joseph Date: Thu, 2 Sep 2021 17:52:28 +0530 Message-ID: <1630585354-1136-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1630585354-1136-1-git-send-email-anoobj@marvell.com> References: <1630585354-1136-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: vDO4Qji8_7K1wDvuwu67XIQq9k9xF0b0 X-Proofpoint-ORIG-GUID: vDO4Qji8_7K1wDvuwu67XIQq9k9xF0b0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-02_04,2021-09-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 1/7] common/cnxk: update to v1.13 ZUC API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vidya Sagar Velumuri Add support for ZUC API change in ucode 1.13 Signed-off-by: Anoob Joseph Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_se.c | 150 ++++++++++++++++++++++++++++++++++++---- drivers/common/cnxk/roc_se.h | 37 +++++++++- drivers/common/cnxk/version.map | 1 + 3 files changed, 172 insertions(+), 16 deletions(-) diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c index b04de79..03fbc5f 100644 --- a/drivers/common/cnxk/roc_se.c +++ b/drivers/common/cnxk/roc_se.c @@ -72,6 +72,11 @@ cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx, fc_type = ROC_SE_FC_GEN; break; case ROC_SE_ZUC_EEA3: + /* No support for chained operations */ + if (unlikely(ctx->hash_type)) + return -1; + fc_type = ROC_SE_PDCP; + break; case ROC_SE_SNOW3G_UEA2: if (unlikely(key_len != 16)) return -1; @@ -123,6 +128,56 @@ cpt_ciph_aes_key_type_set(struct roc_se_context *fctx, uint16_t key_len) fctx->enc.aes_key = aes_key_type; } +static int +cpt_pdcp_key_type_set(struct roc_se_zuc_snow3g_ctx *zs_ctx, uint16_t key_len) +{ + roc_se_aes_type key_type = 0; + + if (roc_model_is_cn9k()) { + if (key_len != 16) { + plt_err("Only key len 16 is supported on cn9k"); + return -ENOTSUP; + } + } + + switch (key_len) { + case 16: + key_type = ROC_SE_AES_128_BIT; + break; + case 32: + key_type = ROC_SE_AES_256_BIT; + break; + default: + plt_err("Invalid AES key len"); + return -ENOTSUP; + } + zs_ctx->zuc.otk_ctx.w0.s.key_len = key_type; + return 0; +} + +static int +cpt_pdcp_mac_len_set(struct roc_se_zuc_snow3g_ctx *zs_ctx, uint16_t mac_len) +{ + roc_se_pdcp_mac_len_type mac_type = 0; + + switch (mac_len) { + case 4: + mac_type = ROC_SE_PDCP_MAC_LEN_32_BIT; + break; + case 8: + mac_type = ROC_SE_PDCP_MAC_LEN_64_BIT; + break; + case 16: + mac_type = ROC_SE_PDCP_MAC_LEN_128_BIT; + break; + default: + plt_err("Invalid ZUC MAC len"); + return -ENOTSUP; + } + zs_ctx->zuc.otk_ctx.w0.s.mac_len = mac_type; + return 0; +} + int roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint8_t *key, uint16_t key_len, uint16_t mac_len) @@ -130,6 +185,7 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, struct roc_se_zuc_snow3g_ctx *zs_ctx; struct roc_se_kasumi_ctx *k_ctx; struct roc_se_context *fctx; + int ret; if (se_ctx == NULL) return -1; @@ -139,32 +195,57 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, fctx = &se_ctx->se_ctx.fctx; if ((type >= ROC_SE_ZUC_EIA3) && (type <= ROC_SE_KASUMI_F9_ECB)) { + uint8_t *zuc_const; uint32_t keyx[4]; + uint8_t *ci_key; - if (key_len != 16) + if (!key_len) return -1; - /* No support for AEAD yet */ + + /* No support for chained operations yet */ if (se_ctx->enc_cipher) return -1; + + if (roc_model_is_cn9k()) { + ci_key = zs_ctx->zuc.onk_ctx.ci_key; + zuc_const = zs_ctx->zuc.onk_ctx.zuc_const; + } else { + ci_key = zs_ctx->zuc.otk_ctx.ci_key; + zuc_const = zs_ctx->zuc.otk_ctx.zuc_const; + } + /* For ZUC/SNOW3G/Kasumi */ switch (type) { case ROC_SE_SNOW3G_UIA2: + zs_ctx->zuc.otk_ctx.w0.s.alg_type = + ROC_SE_PDCP_ALG_TYPE_SNOW3G; + zs_ctx->zuc.otk_ctx.w0.s.mac_len = + ROC_SE_PDCP_MAC_LEN_32_BIT; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_SNOW3G; cpt_snow3g_key_gen(key, keyx); - memcpy(zs_ctx->ci_key, keyx, key_len); + memcpy(ci_key, keyx, key_len); se_ctx->fc_type = ROC_SE_PDCP; se_ctx->zsk_flags = 0x1; break; case ROC_SE_ZUC_EIA3: + zs_ctx->zuc.otk_ctx.w0.s.alg_type = + ROC_SE_PDCP_ALG_TYPE_ZUC; + ret = cpt_pdcp_mac_len_set(zs_ctx, mac_len); + if (ret) + return ret; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC; - memcpy(zs_ctx->ci_key, key, key_len); - memcpy(zs_ctx->zuc_const, zuc_d, 32); + memcpy(ci_key, key, key_len); + memcpy(zuc_const, zuc_d, 32); se_ctx->fc_type = ROC_SE_PDCP; se_ctx->zsk_flags = 0x1; break; case ROC_SE_AES_CMAC_EIA2: + zs_ctx->zuc.otk_ctx.w0.s.alg_type = + ROC_SE_PDCP_ALG_TYPE_AES_CTR; + zs_ctx->zuc.otk_ctx.w0.s.mac_len = + ROC_SE_PDCP_MAC_LEN_32_BIT; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_AES_CTR; - memcpy(zs_ctx->ci_key, key, key_len); + memcpy(ci_key, key, key_len); se_ctx->fc_type = ROC_SE_PDCP; se_ctx->zsk_flags = 0x1; break; @@ -183,8 +264,13 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, default: return -1; } - se_ctx->mac_len = 4; + se_ctx->mac_len = mac_len; se_ctx->hash_type = type; + if (roc_model_is_cn9k()) + se_ctx->template_w4.s.opcode_minor = + ((1 << 7) | (se_ctx->pdcp_alg_type << 5) | 1); + else + se_ctx->template_w4.s.opcode_minor = ((1 << 4) | 1); return 0; } @@ -227,11 +313,21 @@ int roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const uint8_t *key, uint16_t key_len, uint8_t *salt) { + struct roc_se_zuc_snow3g_ctx *zs_ctx = &se_ctx->se_ctx.zs_ctx; struct roc_se_context *fctx = &se_ctx->se_ctx.fctx; - struct roc_se_zuc_snow3g_ctx *zs_ctx; + uint8_t *zuc_const; uint32_t keyx[4]; + uint8_t *ci_key; int ret; + if (roc_model_is_cn9k()) { + ci_key = zs_ctx->zuc.onk_ctx.ci_key; + zuc_const = zs_ctx->zuc.onk_ctx.zuc_const; + } else { + ci_key = zs_ctx->zuc.otk_ctx.ci_key; + zuc_const = zs_ctx->zuc.otk_ctx.zuc_const; + } + /* For AES-GCM, salt is taken from ctx even if IV source * is from DPTR */ @@ -301,21 +397,29 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, memcpy(fctx->hmac.ipad, &key[key_len], key_len); break; case ROC_SE_SNOW3G_UEA2: + zs_ctx->zuc.otk_ctx.w0.s.key_len = ROC_SE_AES_128_BIT; + zs_ctx->zuc.otk_ctx.w0.s.alg_type = ROC_SE_PDCP_ALG_TYPE_SNOW3G; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_SNOW3G; cpt_snow3g_key_gen(key, keyx); - memcpy(se_ctx->se_ctx.zs_ctx.ci_key, keyx, key_len); + memcpy(ci_key, keyx, key_len); se_ctx->zsk_flags = 0; goto success; case ROC_SE_ZUC_EEA3: - zs_ctx = &se_ctx->se_ctx.zs_ctx; + ret = cpt_pdcp_key_type_set(zs_ctx, key_len); + if (ret) + return ret; + zs_ctx->zuc.otk_ctx.w0.s.alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC; - memcpy(zs_ctx->ci_key, key, key_len); - memcpy(zs_ctx->zuc_const, zuc_d, 32); + memcpy(ci_key, key, key_len); + memcpy(zuc_const, zuc_d, 32); se_ctx->zsk_flags = 0; goto success; case ROC_SE_AES_CTR_EEA2: + zs_ctx->zuc.otk_ctx.w0.s.key_len = ROC_SE_AES_128_BIT; + zs_ctx->zuc.otk_ctx.w0.s.alg_type = + ROC_SE_PDCP_ALG_TYPE_AES_CTR; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_AES_CTR; - memcpy(se_ctx->se_ctx.zs_ctx.ci_key, key, key_len); + memcpy(ci_key, key, key_len); se_ctx->zsk_flags = 0; goto success; case ROC_SE_KASUMI_F8_ECB: @@ -341,6 +445,24 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, success: se_ctx->enc_cipher = type; - + if (se_ctx->fc_type == ROC_SE_PDCP) { + if (roc_model_is_cn9k()) + se_ctx->template_w4.s.opcode_minor = + ((1 << 7) | (se_ctx->pdcp_alg_type << 5) | + (se_ctx->zsk_flags & 0x7)); + else + se_ctx->template_w4.s.opcode_minor = ((1 << 4)); + } return 0; } + +void +roc_se_ctx_swap(struct roc_se_ctx *se_ctx) +{ + struct roc_se_zuc_snow3g_ctx *zs_ctx = &se_ctx->se_ctx.zs_ctx; + + if (roc_model_is_cn9k()) + return; + + zs_ctx->zuc.otk_ctx.w0.u64 = htobe64(zs_ctx->zuc.otk_ctx.w0.u64); +} diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index 5c7e2ca..051d496 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -158,6 +158,12 @@ typedef enum { ROC_SE_AES_256_BIT = 0x3 } roc_se_aes_type; +typedef enum { + ROC_SE_PDCP_MAC_LEN_32_BIT = 0x1, + ROC_SE_PDCP_MAC_LEN_64_BIT = 0x2, + ROC_SE_PDCP_MAC_LEN_128_BIT = 0x3 +} roc_se_pdcp_mac_len_type; + struct roc_se_sglist_comp { union { uint64_t len; @@ -192,12 +198,35 @@ struct roc_se_context { struct roc_se_hmac_context hmac; }; -struct roc_se_zuc_snow3g_ctx { +struct roc_se_otk_zuc_ctx { + union { + uint64_t u64; + struct { + uint64_t rsvd_56 : 57; + uint64_t mac_len : 2; + uint64_t key_len : 2; + uint64_t lfsr_state : 1; + uint64_t alg_type : 2; + } s; + } w0; + uint8_t ci_key[32]; + uint8_t encr_auth_iv[24]; + uint8_t zuc_const[32]; +}; + +struct roc_se_onk_zuc_ctx { uint8_t encr_auth_iv[16]; uint8_t ci_key[16]; uint8_t zuc_const[32]; }; +struct roc_se_zuc_snow3g_ctx { + union { + struct roc_se_onk_zuc_ctx onk_ctx; + struct roc_se_otk_zuc_ctx otk_ctx; + } zuc; +}; + struct roc_se_kasumi_ctx { uint8_t reg_A[8]; uint8_t ci_key[16]; @@ -229,7 +258,10 @@ struct roc_se_fc_params { void *auth_iv_buf; struct roc_se_buf_ptr meta_buf; struct roc_se_buf_ptr ctx_buf; - uint64_t rsvd2; + uint32_t rsvd2; + uint16_t rsvd3; + uint8_t cipher_iv_len; + uint8_t auth_iv_len; /* 1st cache line */ struct roc_se_buf_ptr aad_buf __plt_cache_aligned; @@ -272,4 +304,5 @@ int __roc_api roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const uint8_t *key, uint16_t key_len, uint8_t *salt); +void __roc_api roc_se_ctx_swap(struct roc_se_ctx *se_ctx); #endif /* __ROC_SE_H__ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 34a844b..5865fc6 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -267,6 +267,7 @@ INTERNAL { roc_tim_lf_disable; roc_tim_lf_enable; roc_tim_lf_free; + roc_se_ctx_swap; local: *; };