diff mbox series

[1/2] build: fix SVE compile error with gcc8.3

Message ID 1624849071-56826-2-git-send-email-fengchengwen@huawei.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers show
Series bugfix for SVE compile | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

fengchengwen June 28, 2021, 2:57 a.m. UTC
If the target machine has SVE feature (e.g. "-march=armv8.2-a+sve'),
and the compiler are gcc8.3, it will compile error:
	In file included from ../dpdk-next-net/lib/eal/common/
	eal_common_options.c:38:
	../dpdk-next-net/lib/eal/arm/include/rte_vect.h:13:10: fatal
	error: arm_sve.h: No such file or directory
	#include <arm_sve.h>
	       ^~~~~~~~~~~
	compilation terminated.

The root cause is that gcc8.3 supports SVE (the macro
__ARM_FEATURE_SVE was 1), but it doesn't support SVE ACLE [1].

The solution:
a) Detect compiler whether support SVE ACLE, if support then define
RTE_HAS_SVE_ACLE macro.
b) Use the RTE_HAS_SVE_ACLE macro to include SVE header file.

[1] ACLE:  Arm C Language Extensions, the SVE ACLE header file is
<arm_sve.h>, user should include it when writing ACLE SVE code.

Fixes: 67b68824a82d ("lpm/arm: support SVE")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 config/arm/meson.build         | 6 ++++++
 lib/eal/arm/include/rte_vect.h | 2 +-
 lib/lpm/rte_lpm.h              | 2 +-
 3 files changed, 8 insertions(+), 2 deletions(-)

Comments

Thomas Monjalon July 9, 2021, 8:18 p.m. UTC | #1
28/06/2021 04:57, Chengwen Feng:
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -488,3 +488,9 @@ if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
>      compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
>      'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
>  endif
> +
> +# Check whether SVE ACLE is supported and set the corresponding flag which will used with SVE ACLE code.
> +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> +        cc.check_header('arm_sve.h'))
> +    dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> +endif

Simpler and better sorted:

--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -524,6 +524,9 @@ endif
 
 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
     compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
+    if (cc.check_header('arm_sve.h'))
+        dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
+    endif
 endif
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index e83a56e..7342626 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -488,3 +488,9 @@  if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
     compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
     'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 endif
+
+# Check whether SVE ACLE is supported and set the corresponding flag which will used with SVE ACLE code.
+if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
+        cc.check_header('arm_sve.h'))
+    dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
+endif
diff --git a/lib/eal/arm/include/rte_vect.h b/lib/eal/arm/include/rte_vect.h
index 093e912..4b705ba 100644
--- a/lib/eal/arm/include/rte_vect.h
+++ b/lib/eal/arm/include/rte_vect.h
@@ -9,7 +9,7 @@ 
 #include "generic/rte_vect.h"
 #include "rte_debug.h"
 #include "arm_neon.h"
-#ifdef __ARM_FEATURE_SVE
+#ifdef RTE_HAS_SVE_ACLE
 #include <arm_sve.h>
 #endif
 
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 28b5768..5eb14c1 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -402,7 +402,7 @@  rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
 	uint32_t defv);
 
 #if defined(RTE_ARCH_ARM)
-#ifdef __ARM_FEATURE_SVE
+#ifdef RTE_HAS_SVE_ACLE
 #include "rte_lpm_sve.h"
 #else
 #include "rte_lpm_neon.h"