From patchwork Fri Jun 25 05:36:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 94811 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6CEBDA0C40; Fri, 25 Jun 2021 07:37:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 31038410F0; Fri, 25 Jun 2021 07:37:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id DD93B40E03 for ; Fri, 25 Jun 2021 07:37:35 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15P5Zjmi016222; Thu, 24 Jun 2021 22:37:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Zw+x9QGf9EkLU57WPLL235/0I1xj5jWDRW4M+ATC3kY=; b=Lc6+VKbfzzxgyg7w6Qa9KGXfHQE3iTdGLhlkLFFl8K5wKylpl+QGPAL874x/5ne3OZgi 2R/+sRM1ofss9fi8bXC2cszrRwtDmbS5isWxDF/WHv8VP9w7PA+ZC7lZAWDTVx1HrO34 hPJ7dJ7FhT06R5bpck0J089fj84+RRUX2qMzRY9siv7zFGrSPmFfO+0RIJFzSFi8RGri LAds+5e3TDdcBF0OD20uRF8PdFwdbEizB7iNcD38Jl3+0bu45IDYyiSewmHldWC7jme5 PKuE02mvkUqHc4MwdLq4W42Pfju1SpEdmVHf0DSLHlRx01Vt7UuQbqWDRtFPwM3/MMFv ig== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39d241sg4g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Jun 2021 22:37:35 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Jun 2021 22:37:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 24 Jun 2021 22:37:33 -0700 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 965533F7041; Thu, 24 Jun 2021 22:37:29 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Vidya Sagar Velumuri , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Aakash Sasidharan Date: Fri, 25 Jun 2021 11:06:37 +0530 Message-ID: <1624599410-29689-6-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624599410-29689-1-git-send-email-anoobj@marvell.com> References: <1624599410-29689-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: qal-x5B-lJGj0LA1K3zM6zFy46l9MDPB X-Proofpoint-ORIG-GUID: qal-x5B-lJGj0LA1K3zM6zFy46l9MDPB X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 Subject: [dpdk-dev] [PATCH v2 05/17] common/cnxk: add mbox to configure RXC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vidya Sagar Velumuri Add mailbox to configure tiemouts and thresholds in CPT RXC unit. Signed-off-by: Aakash Sasidharan Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_cpt.c | 27 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 10 ++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 38 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index d891a3b..e723ee7 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -6,6 +6,33 @@ #include "roc_priv.h" int +roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct cpt_rxc_time_cfg_req *req; + struct dev *dev = &cpt->dev; + + req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox); + if (req == NULL) + return -ENOSPC; + + req->blkaddr = 0; + + /* The step value is in microseconds. */ + req->step = cfg->step; + + /* The timeout will be: limit * step microseconds */ + req->zombie_limit = cfg->zombie_limit; + req->zombie_thres = cfg->zombie_thres; + + /* The timeout will be: limit * step microseconds */ + req->active_limit = cfg->active_limit; + req->active_thres = cfg->active_thres; + + return mbox_process(dev->mbox); +} + +int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp) { struct mbox *mbox = dev->mbox; diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 4e1cf84..bae472f 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -28,6 +28,16 @@ struct roc_cpt { uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; +struct roc_cpt_rxc_time_cfg { + uint32_t step; + uint16_t active_limit; + uint16_t active_thres; + uint16_t zombie_limit; + uint16_t zombie_thres; +}; + +int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, + struct roc_cpt_rxc_time_cfg *cfg); int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index f36127c..13fd026 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -16,6 +16,7 @@ INTERNAL { roc_cpt_dev_fini; roc_cpt_dev_init; roc_cpt_eng_grp_add; + roc_cpt_rxc_time_cfg; roc_error_msg_get; roc_idev_cpt_get; roc_idev_cpt_set;