diff mbox series

[v2,01/17] common/cnxk: add CPT HW defines

Message ID 1624599410-29689-2-git-send-email-anoobj@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers show
Series Add CPT in Marvell CNXK common driver | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Anoob Joseph June 25, 2021, 5:36 a.m. UTC
From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Add CPT hardware definitions. CPT is the hardware block on
cnxk family of processors, that can be used to offload
cryptographic operations.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>

---
 drivers/common/cnxk/hw/cpt.h  | 291 ++++++++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_api.h |   6 +
 2 files changed, 297 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/cpt.h
diff mbox series

Patch

diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
new file mode 100644
index 0000000..84ebf2d
--- /dev/null
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -0,0 +1,291 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __CPT_HW_H__
+#define __CPT_HW_H__
+
+/* Register offsets */
+
+#define CPT_COMP_NOT_DONE (0x0ull)
+#define CPT_COMP_GOOD	  (0x1ull)
+#define CPT_COMP_FAULT	  (0x2ull)
+#define CPT_COMP_SWERR	  (0x3ull)
+#define CPT_COMP_HWERR	  (0x4ull)
+#define CPT_COMP_INSTERR  (0x5ull)
+#define CPT_COMP_WARN	  (0x6ull) /* [CN10K, .) */
+
+#define CPT_LF_INT_VEC_MISC	(0x0ull)
+#define CPT_LF_INT_VEC_DONE	(0x1ull)
+#define CPT_LF_CTL		(0x10ull)
+#define CPT_LF_DONE_WAIT	(0x30ull)
+#define CPT_LF_INPROG		(0x40ull)
+#define CPT_LF_DONE		(0x50ull)
+#define CPT_LF_DONE_ACK		(0x60ull)
+#define CPT_LF_DONE_INT_ENA_W1S (0x90ull)
+#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull)
+#define CPT_LF_MISC_INT		(0xb0ull)
+#define CPT_LF_MISC_INT_W1S	(0xc0ull)
+#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull)
+#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull)
+#define CPT_LF_Q_BASE		(0xf0ull)
+#define CPT_LF_Q_SIZE		(0x100ull)
+#define CPT_LF_Q_INST_PTR	(0x110ull)
+#define CPT_LF_Q_GRP_PTR	(0x120ull)
+#define CPT_LF_NQX(a)		(0x400ull | (uint64_t)(a) << 3)
+#define CPT_LF_CTX_CTL		(0x500ull)
+#define CPT_LF_CTX_FLUSH	(0x510ull)
+#define CPT_LF_CTX_ERR		(0x520ull)
+#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull)
+#define CPT_LF_CTX_ENC_PKT_CNT	(0x540ull)
+#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)
+#define CPT_LF_CTX_DEC_PKT_CNT	(0x560ull)
+
+#define CPT_AF_LFX_CTL(a)  (0x27000ull | (uint64_t)(a) << 3)
+#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
+
+/* Structures definitions */
+
+union cpt_lf_ctl {
+	uint64_t u;
+	struct cpt_lf_ctl_s {
+		uint64_t ena : 1;
+		uint64_t fc_ena : 1;
+		uint64_t fc_up_crossing : 1;
+		uint64_t reserved_3_3 : 1;
+		uint64_t fc_hyst_bits : 4;
+		uint64_t reserved_8_63 : 56;
+	} s;
+};
+
+union cpt_lf_ctx_flush {
+	uint64_t u;
+	struct {
+		uint64_t cptr : 46;
+		uint64_t inval : 1;
+		uint64_t res : 1;
+		uint64_t pf_func : 16;
+	} s;
+};
+
+union cpt_lf_inprog {
+	uint64_t u;
+	struct cpt_lf_inprog_s {
+		uint64_t inflight : 9;
+		uint64_t reserved_9_15 : 7;
+		uint64_t eena : 1;
+		uint64_t grp_drp : 1;
+		uint64_t reserved_18_30 : 13;
+		uint64_t grb_partial : 1;
+		uint64_t grb_cnt : 8;
+		uint64_t gwb_cnt : 8;
+		uint64_t reserved_48_63 : 16;
+	} s;
+};
+
+union cpt_lf_q_base {
+	uint64_t u;
+	struct cpt_lf_q_base_s {
+		uint64_t fault : 1;
+		uint64_t stopped : 1;
+		uint64_t reserved_2_6 : 5;
+		uint64_t addr : 46;
+		uint64_t reserved_53_63 : 11;
+	} s;
+};
+
+union cpt_lf_q_size {
+	uint64_t u;
+	struct cpt_lf_q_size_s {
+		uint64_t size_div40 : 15;
+		uint64_t reserved_15_63 : 49;
+	} s;
+};
+
+union cpt_lf_misc_int {
+	uint64_t u;
+	struct cpt_lf_misc_int_s {
+		uint64_t reserved_0_0 : 1;
+		uint64_t nqerr : 1;
+		uint64_t irde : 1;
+		uint64_t nwrp : 1;
+		uint64_t reserved_4_4 : 1;
+		uint64_t hwerr : 1;
+		uint64_t fault : 1;
+		uint64_t reserved_7_63 : 57;
+	} s;
+};
+
+union cpt_inst_w4 {
+	uint64_t u64;
+	struct {
+		uint64_t dlen : 16;
+		uint64_t param2 : 16;
+		uint64_t param1 : 16;
+		uint64_t opcode_major : 8;
+		uint64_t opcode_minor : 8;
+	} s;
+};
+
+union cpt_inst_w7 {
+	uint64_t u64;
+	struct {
+		uint64_t cptr : 60;
+		uint64_t ctx_val : 1;
+		uint64_t egrp : 3;
+	} s;
+};
+
+struct cpt_inst_s {
+	union cpt_inst_w0 {
+		struct {
+			uint64_t nixtxl : 3;
+			uint64_t doneint : 1;
+			uint64_t nixtx_addr : 60;
+		} s;
+		uint64_t u64;
+	} w0;
+
+	uint64_t res_addr;
+
+	union cpt_inst_w2 {
+		struct {
+			uint64_t tag : 32;
+			uint64_t tt : 2;
+			uint64_t grp : 10;
+			uint64_t reserved_172_175 : 4;
+			uint64_t rvu_pf_func : 16;
+		} s;
+		uint64_t u64;
+	} w2;
+
+	union cpt_inst_w3 {
+		struct {
+			uint64_t qord : 1;
+			uint64_t reserved_194_193 : 2;
+			uint64_t wqe_ptr : 61;
+		} s;
+		uint64_t u64;
+	} w3;
+
+	union cpt_inst_w4 w4;
+
+	uint64_t dptr;
+
+	uint64_t rptr;
+
+	union cpt_inst_w7 w7;
+};
+
+union cpt_res_s {
+	struct cpt_cn10k_res_s {
+		uint64_t compcode : 7;
+		uint64_t doneint : 1;
+		uint64_t uc_compcode : 8;
+		uint64_t rlen : 16;
+		uint64_t spi : 32;
+
+		uint64_t esn;
+	} cn10k;
+
+	struct cpt_cn9k_res_s {
+		uint64_t compcode : 8;
+		uint64_t uc_compcode : 8;
+		uint64_t doneint : 1;
+		uint64_t reserved_17_63 : 47;
+
+		uint64_t reserved_64_127;
+	} cn9k;
+};
+
+/* [CN10K, .) */
+struct cpt_parse_hdr_s {
+	/* WORD 0 */
+	union {
+		uint64_t u64;
+		struct {
+			uint8_t pad_len : 3;
+			uint8_t num_frags : 3;
+			uint8_t pkt_out : 2;
+
+			uint8_t err_sum : 1;
+			uint8_t reas_sts : 4;
+			uint8_t reserved_53 : 1;
+			uint8_t et_owr : 1;
+			uint8_t pkt_fmt : 1;
+
+			uint16_t match_id : 16;
+
+			uint32_t cookie : 32;
+		};
+	} w0;
+
+	/* WORD 1 */
+	uint64_t wqe_ptr;
+
+	/* WORD 2 */
+	union {
+		uint64_t u64;
+		struct {
+			uint8_t fi_pad : 3;
+			uint8_t fi_offset : 5;
+			uint8_t il3_off;
+			uint16_t orig_pf_func;
+			uint16_t reserved_145_160;
+			uint16_t frag_age;
+		};
+	} w2;
+
+	/* WORD 3 */
+	union {
+		uint64_t u64;
+		struct {
+			uint32_t spi;
+			uint16_t reserved_209_224;
+			uint8_t uc_ccode;
+			uint8_t hw_ccode;
+		};
+	} w3;
+
+	/* WORD 4 */
+	union {
+		uint64_t u64;
+		uint64_t esn;
+		uint64_t frag1_wqe_ptr;
+	};
+};
+
+union cpt_frag_info {
+	uint16_t info;
+	struct {
+		uint16_t f_off : 13;
+		uint16_t f_mf : 1;
+		uint16_t f_rsv : 2;
+	};
+};
+
+struct cpt_frag_info_s {
+	/* WORD 0 */
+	union {
+		uint64_t u64;
+		struct {
+			union cpt_frag_info f3;
+			union cpt_frag_info f2;
+			union cpt_frag_info f1;
+			union cpt_frag_info f0;
+		};
+	} w0;
+
+	/* WORD 1 */
+	union {
+		uint64_t u64;
+		struct {
+			uint16_t frag_size3;
+			uint16_t frag_size2;
+			uint16_t frag_size1;
+			uint16_t frag_size0;
+		};
+	} w1;
+};
+
+#endif /* __CPT_HW_H__ */
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 67f5d13..049854d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -54,6 +54,11 @@ 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
 
+#define PCI_DEVID_CN9K_RVU_CPT_PF  0xA0FD
+#define PCI_DEVID_CN9K_RVU_CPT_VF  0xA0FE
+#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2
+#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3
+
 #define PCI_SUBSYSTEM_DEVID_CN10KA  0xB900
 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
 
@@ -64,6 +69,7 @@ 
 #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100
 
 /* HW structure definition */
+#include "hw/cpt.h"
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"