diff mbox series

[17/20] crypto/cnxk: add KASUMI encrypt

Message ID 1622652221-22732-18-git-send-email-anoobj@marvell.com (mailing list archive)
State Superseded
Delegated to: akhil goyal
Headers show
Series Add Marvell CNXK crypto PMDs | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Anoob Joseph June 2, 2021, 4:43 p.m. UTC
From: Tejasree Kondoj <ktejasree@marvell.com>

Add KASUMI encrypt support.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 doc/guides/cryptodevs/features/cn10k.ini |   1 +
 doc/guides/cryptodevs/features/cn9k.ini  |   1 +
 drivers/crypto/cnxk/cnxk_se.h            | 196 +++++++++++++++++++++++++++++++
 3 files changed, 198 insertions(+)

Comments

Akhil Goyal June 16, 2021, 7:51 p.m. UTC | #1
> diff --git a/doc/guides/cryptodevs/features/cn10k.ini
> b/doc/guides/cryptodevs/features/cn10k.ini
> index 8f20d07..23ec100 100644
> --- a/doc/guides/cryptodevs/features/cn10k.ini
> +++ b/doc/guides/cryptodevs/features/cn10k.ini
> @@ -30,6 +30,7 @@ AES CTR (256)  = Y
>  AES XTS (128)  = Y
>  AES XTS (256)  = Y
>  DES CBC        = Y
> +KASUMI F8      = Y
>  SNOW3G UEA2    = Y
>  ZUC EEA3       = Y
> 
Same comment as in 15/20 patch.
diff mbox series

Patch

diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini
index 8f20d07..23ec100 100644
--- a/doc/guides/cryptodevs/features/cn10k.ini
+++ b/doc/guides/cryptodevs/features/cn10k.ini
@@ -30,6 +30,7 @@  AES CTR (256)  = Y
 AES XTS (128)  = Y
 AES XTS (256)  = Y
 DES CBC        = Y
+KASUMI F8      = Y
 SNOW3G UEA2    = Y
 ZUC EEA3       = Y
 
diff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini
index fb0c09b..e833dc0 100644
--- a/doc/guides/cryptodevs/features/cn9k.ini
+++ b/doc/guides/cryptodevs/features/cn9k.ini
@@ -30,6 +30,7 @@  AES CTR (256)  = Y
 AES XTS (128)  = Y
 AES XTS (256)  = Y
 DES CBC        = Y
+KASUMI F8      = Y
 SNOW3G UEA2    = Y
 ZUC EEA3       = Y
 
diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
index b23fbd6..c0e5cff 100644
--- a/drivers/crypto/cnxk/cnxk_se.h
+++ b/drivers/crypto/cnxk/cnxk_se.h
@@ -1565,6 +1565,199 @@  cpt_zuc_snow3g_dec_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 }
 
 static __rte_always_inline int
+cpt_kasumi_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
+		    struct roc_se_fc_params *params, struct cpt_inst_s *inst)
+{
+	void *m_vaddr = params->meta_buf.vaddr;
+	uint32_t size;
+	int32_t inputlen = 0, outputlen = 0;
+	struct roc_se_ctx *se_ctx;
+	uint32_t mac_len = 0;
+	uint8_t i = 0;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len;
+	int flags;
+	uint8_t *iv_s, *iv_d, iv_len = 8;
+	uint8_t dir = 0;
+	uint64_t *offset_vaddr;
+	union cpt_inst_w4 cpt_inst_w4;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	struct roc_se_sglist_comp *gather_comp;
+	struct roc_se_sglist_comp *scatter_comp;
+
+	encr_offset = ROC_SE_ENCR_OFFSET(d_offs) / 8;
+	auth_offset = ROC_SE_AUTH_OFFSET(d_offs) / 8;
+	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);
+	auth_data_len = ROC_SE_AUTH_DLEN(d_lens);
+
+	se_ctx = params->ctx_buf.vaddr;
+	flags = se_ctx->zsk_flags;
+	mac_len = se_ctx->mac_len;
+
+	if (flags == 0x0)
+		iv_s = params->iv_buf;
+	else
+		iv_s = params->auth_iv_buf;
+
+	dir = iv_s[8] & 0x1;
+
+	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_KASUMI | ROC_SE_DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	cpt_inst_w4.s.opcode_minor = ((1 << 6) | (se_ctx->k_ecb << 5) |
+				      (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	cpt_inst_w4.s.param1 = encr_data_len;
+	cpt_inst_w4.s.param2 = auth_data_len;
+
+	/* consider iv len */
+	if (flags == 0x0) {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* save space for offset ctrl and iv */
+	offset_vaddr = m_vaddr;
+
+	m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+
+	if (flags == 0x0) {
+		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+		if (unlikely((encr_offset >> 16))) {
+			CPT_LOG_DP_ERR("Offset not supported");
+			CPT_LOG_DP_ERR("enc_offset: %d", encr_offset);
+			return -1;
+		}
+	} else {
+		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
+		if (unlikely((auth_offset >> 8))) {
+			CPT_LOG_DP_ERR("Offset not supported");
+			CPT_LOG_DP_ERR("auth_offset: %d", auth_offset);
+			return -1;
+		}
+	}
+
+	i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
+			 ROC_SE_OFF_CTRL_LEN + iv_len);
+
+	/* IV */
+	iv_d = (uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN;
+	memcpy(iv_d, iv_s, iv_len);
+
+	/* input data */
+	size = inputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0,
+					  &size, NULL, 0);
+
+		if (unlikely(size)) {
+			CPT_LOG_DP_ERR("Insufficient buffer space,"
+				       " size %d needed",
+				       size);
+			return -1;
+		}
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp = (struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
+						     g_size_bytes);
+
+	if (flags == 0x1) {
+		/* IV in SLIST only for F8 */
+		iv_len = 0;
+	}
+
+	/* IV */
+	if (iv_len) {
+		i = fill_sg_comp(scatter_comp, i,
+				 (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN,
+				 iv_len);
+	}
+
+	/* Add output data */
+	if (req_flags & ROC_SE_VALID_MAC_BUF) {
+		size = outputlen - iv_len - mac_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0, &size,
+						  NULL, 0);
+
+			if (unlikely(size)) {
+				CPT_LOG_DP_ERR("Insufficient buffer space,"
+					       " size %d needed",
+					       size);
+				return -1;
+			}
+		}
+
+		/* mac data */
+		if (mac_len) {
+			i = fill_sg_comp_from_buf(scatter_comp, i,
+						  &params->mac_buf);
+		}
+	} else {
+		/* Output including mac */
+		size = outputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0, &size,
+						  NULL, 0);
+
+			if (unlikely(size)) {
+				CPT_LOG_DP_ERR("Insufficient buffer space,"
+					       " size %d needed",
+					       size);
+				return -1;
+			}
+		}
+	}
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);
+
+	size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len in case of SG mode */
+	cpt_inst_w4.s.dlen = size;
+
+	inst->dptr = (uint64_t)in_buffer;
+	inst->w4.u64 = cpt_inst_w4.u64;
+
+	return 0;
+}
+
+static __rte_always_inline int
 cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 		     struct roc_se_fc_params *fc_params,
 		     struct cpt_inst_s *inst)
@@ -1600,6 +1793,9 @@  cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	} else if (fc_type == ROC_SE_PDCP) {
 		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params,
 					      inst);
+	} else if (fc_type == ROC_SE_KASUMI) {
+		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params,
+					  inst);
 	}
 
 	return ret;