From patchwork Wed Jun 2 15:56:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93799 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D82D9A0524; Wed, 2 Jun 2021 17:57:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 46DCF410EE; Wed, 2 Jun 2021 17:57:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7803D410F2 for ; Wed, 2 Jun 2021 17:57:01 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpJON019770; Wed, 2 Jun 2021 08:57:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Ic8Oro3x/8JlMbJzG/0c5mjzmkJZrL0f515jxca5NOQ=; b=Ii0dvg1VkNmIlqevQXurD4f3z9KoxVVfhjhtRD3EYjhHCw4PspI2B7ZENR5y5k30eynb 8UDgGAWTtK/hvWn3Iy/tjIrd8+k4GORWBozO/bwitVteGVuvZ8Z376ZOOc1Df0+cIhCD ocFsYJefYpZ+x5dxiW1mJgucaMzQrn2J16cEFM87SEzS/RjtGcjOGh5gAM46qCBO3NpB kM6FoI1Akky5bY4KGyNqq+ZaYaf1p+2ZTBR7d8TMFK0g6fIrQEpCUQY9CbRYoA0QNRpd N5GO5RjtU3wmmVbUivbnc7fZfAVpNB+xC0aCb8km2p7Uz7sqQzpi2dPqVbX13jFH7lRH OQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38wufguhbs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 08:57:00 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:56:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:56:58 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 660463F703F; Wed, 2 Jun 2021 08:56:55 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Vidya Sagar Velumuri , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Aakash Sasidharan Date: Wed, 2 Jun 2021 21:26:17 +0530 Message-ID: <1622649385-22652-4-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: wxJm6A3hQJ2jmzuGjDEn_iD-zn5fcjJr X-Proofpoint-GUID: wxJm6A3hQJ2jmzuGjDEn_iD-zn5fcjJr X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 03/11] common/cnxk: add mbox to configure RXC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vidya Sagar Velumuri Add mailbox to configure tiemouts and thresholds in CPT RXC unit. Signed-off-by: Aakash Sasidharan Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_cpt.c | 27 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 10 ++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 38 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 3c0683c..11d8b9d 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -5,6 +5,33 @@ #include "roc_api.h" #include "roc_priv.h" +int +roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct cpt_rxc_time_cfg_req *req; + struct dev *dev = &cpt->dev; + + req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox); + if (req == NULL) + return -ENOSPC; + + req->blkaddr = 0; + + /* The step value is in microseconds. */ + req->step = cfg->step; + + /* The timeout will be: limit * step microseconds */ + req->zombie_limit = cfg->zombie_limit; + req->zombie_thres = cfg->zombie_thres; + + /* The timeout will be: limit * step microseconds */ + req->active_limit = cfg->active_limit; + req->active_thres = cfg->active_thres; + + return mbox_process(dev->mbox); +} + static int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp) { diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 2630955..5b84ec5 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -23,6 +23,16 @@ struct roc_cpt { uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; +struct roc_cpt_rxc_time_cfg { + uint32_t step; + uint16_t active_limit; + uint16_t active_thres; + uint16_t zombie_limit; + uint16_t zombie_thres; +}; + +int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, + struct roc_cpt_rxc_time_cfg *cfg); int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index f8e286e..1dbeebe 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -16,6 +16,7 @@ INTERNAL { roc_cpt_dev_fini; roc_cpt_dev_init; roc_cpt_eng_grp_add; + roc_cpt_rxc_time_cfg; roc_error_msg_get; roc_idev_lmt_base_addr_get; roc_idev_npa_maxpools_get;