From patchwork Wed Jun 2 15:56:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93805 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F23CA0524; Wed, 2 Jun 2021 17:57:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B416410FC; Wed, 2 Jun 2021 17:57:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AE05F4069F for ; Wed, 2 Jun 2021 17:57:31 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpJqk019768; Wed, 2 Jun 2021 08:57:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=wb6/QjdqqF7gUh6/gZUAMsZ2Y/6lPYtrmcaanlFhC28=; b=YHPm/TNpYnHQ12IOyO7sW8botM5IcXXKLjSQkwrdhsKFtn5Ptj6daJSrEX/ZhRIHc0Ju 096Pq6qfinRPGJ7ltriuVEutCySbCOnk85c0Yr+SeY6q6L0ry2+f2U60tN7OUSakeRr9 09NzOawYZdpnx7v0hYHC7RMiDuM2B6mPKLbBN5XPO/GVlS4RMHY555DTBK/RxRpyJkfX qV93jQifkL4+xsNSZwjaZ8b5/odm0d9GL1DFuAl1A4V4V9AU/V7U8NevYiOLOR1CybAM AIK585puLkElB57Jt/2kt/165+WXAROqeYJHFtp1IRX/3Vq/NPxaJmxIUh1pIfutCGWH Hg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38wufguhf3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 08:57:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:57:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:29 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id C74053F703F; Wed, 2 Jun 2021 08:57:25 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Kiran Kumar Kokkilagadda , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Wed, 2 Jun 2021 21:26:23 +0530 Message-ID: <1622649385-22652-10-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dIq2iZkImarahxLhGu0xtBNlY918_W_i X-Proofpoint-GUID: dIq2iZkImarahxLhGu0xtBNlY918_W_i X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 09/11] common/cnxk: add AE microcode defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar Kokkilagadda Microcode AE opcodes support asymmetric operations. Add defines and structs defined by microcode. Signed-off-by: Anoob Joseph Signed-off-by: Kiran Kumar Kokkilagadda --- drivers/common/cnxk/roc_ae.h | 56 +++++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 3 +++ 2 files changed, 59 insertions(+) create mode 100644 drivers/common/cnxk/roc_ae.h diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h new file mode 100644 index 0000000..c549e18 --- /dev/null +++ b/drivers/common/cnxk/roc_ae.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __ROC_AE_H__ +#define __ROC_AE_H__ + +/* AE opcodes */ +#define ROC_AE_MAJOR_OP_MODEX 0x03 +#define ROC_AE_MAJOR_OP_ECDSA 0x04 +#define ROC_AE_MAJOR_OP_ECC 0x05 +#define ROC_AE_MINOR_OP_MODEX 0x01 +#define ROC_AE_MINOR_OP_PKCS_ENC 0x02 +#define ROC_AE_MINOR_OP_PKCS_ENC_CRT 0x03 +#define ROC_AE_MINOR_OP_PKCS_DEC 0x04 +#define ROC_AE_MINOR_OP_PKCS_DEC_CRT 0x05 +#define ROC_AE_MINOR_OP_MODEX_CRT 0x06 +#define ROC_AE_MINOR_OP_ECDSA_SIGN 0x01 +#define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02 +#define ROC_AE_MINOR_OP_ECC_UMP 0x03 + +/** + * Enumeration roc_ae_ec_id + * + * Enumerates supported elliptic curves + */ +typedef enum { + ROC_AE_EC_ID_P192 = 0, + ROC_AE_EC_ID_P224 = 1, + ROC_AE_EC_ID_P256 = 2, + ROC_AE_EC_ID_P384 = 3, + ROC_AE_EC_ID_P521 = 4, + ROC_AE_EC_ID_PMAX = 5 +} roc_ae_ec_id; + +/* Prime and order fields of built-in elliptic curves */ +struct roc_ae_ec_group { + struct { + /* P521 maximum length */ + uint8_t data[66]; + unsigned int length; + } prime; + + struct { + /* P521 maximum length */ + uint8_t data[66]; + unsigned int length; + } order; +}; + +struct roc_ae_ec_ctx { + /* Prime length defined by microcode for EC operations */ + uint8_t curveid; +}; + +#endif /* __ROC_AE_H__ */ diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 2b43a5a..1e7a208 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -7,6 +7,9 @@ #include "roc_api.h" +#define ROC_AE_CPT_BLOCK_TYPE1 0 +#define ROC_AE_CPT_BLOCK_TYPE2 1 + #define ROC_CPT_MAX_LFS 64 struct roc_cpt_lf {