From patchwork Wed May 12 18:24:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 93235 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6286A0C41; Wed, 12 May 2021 20:24:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D7FD4003F; Wed, 12 May 2021 20:24:59 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 7FA374003E for ; Wed, 12 May 2021 20:24:55 +0200 (CEST) IronPort-SDR: bfd4SoqFQiaR48hySNQ1g6YjeQgV+BujJcfQ5y4XYGkn1QD6mdv4titLUh44YfFs/gv6/zNb/A B+pCMakmmCmw== X-IronPort-AV: E=McAfee;i="6200,9189,9982"; a="285280781" X-IronPort-AV: E=Sophos;i="5.82,293,1613462400"; d="scan'208";a="285280781" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2021 11:24:53 -0700 IronPort-SDR: xBh0nHtxXvht2AF2ucaaWS/K2YlssyWvxEqT8pUfDrvI13wtOvwFP6re6+zaj9lS9cN3oAXZrD vP1RkHKibhEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,293,1613462400"; d="scan'208";a="625528948" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by fmsmga005.fm.intel.com with ESMTP; 12 May 2021 11:24:52 -0700 From: "McDaniel, Timothy" To: Cc: dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net, Timothy McDaniel Date: Wed, 12 May 2021 13:24:48 -0500 Message-Id: <1620843888-882873-1-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 Subject: [dpdk-dev] [PATCH 1/1] event/dlb2: fix vector based dequeue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Timothy McDaniel This commit fixes the following bugs in the vector based dequeue path: - extract hw sched type - update xstats The default mode of operation was also changed from vector optimized mode to scalar mode. Fixes: 000a7b8e7582 ("event/dlb2: optimize dequeue operation") Cc: timothy.mcdaniel@intel.com Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2.c | 40 ++++++++++++++++++++++++---------- drivers/event/dlb2/dlb2_priv.h | 7 +++--- 2 files changed, 31 insertions(+), 16 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 3570678b9..b5745f6f4 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -376,11 +376,11 @@ set_default_depth_thresh(const char *key __rte_unused, } static int -set_vector_opts_disab(const char *key __rte_unused, +set_vector_opts_enab(const char *key __rte_unused, const char *value, void *opaque) { - bool *dlb2_vector_opts_disabled = opaque; + bool *dlb2_vector_opts_enabled = opaque; if (value == NULL || opaque == NULL) { DLB2_LOG_ERR("NULL pointer\n"); @@ -388,9 +388,9 @@ set_vector_opts_disab(const char *key __rte_unused, } if ((*value == 'y') || (*value == 'Y')) - *dlb2_vector_opts_disabled = true; + *dlb2_vector_opts_enabled = true; else - *dlb2_vector_opts_disabled = false; + *dlb2_vector_opts_enabled = false; return 0; } @@ -1469,7 +1469,7 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2, #else if ((qm_port->cq_depth > 64) || (!rte_is_power_of_2(qm_port->cq_depth)) || - (dlb2->vector_opts_disabled == true)) + (dlb2->vector_opts_enabled == false)) qm_port->use_scalar = true; #endif @@ -1665,7 +1665,7 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2, #else if ((qm_port->cq_depth > 64) || (!rte_is_power_of_2(qm_port->cq_depth)) || - (dlb2->vector_opts_disabled == true)) + (dlb2->vector_opts_enabled == false)) qm_port->use_scalar = true; #endif @@ -3561,6 +3561,11 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port, int ev_qid2 = qm_port->qid_mappings[hw_qid2]; int ev_qid3 = qm_port->qid_mappings[hw_qid3]; + int hw_sched0 = _mm_extract_epi8(v_qe_meta, 3) & 3ul; + int hw_sched1 = _mm_extract_epi8(v_qe_meta, 7) & 3ul; + int hw_sched2 = _mm_extract_epi8(v_qe_meta, 11) & 3ul; + int hw_sched3 = _mm_extract_epi8(v_qe_meta, 15) & 3ul; + v_qid_done = _mm_insert_epi8(v_qid_done, ev_qid0, 2); v_qid_done = _mm_insert_epi8(v_qid_done, ev_qid1, 6); v_qid_done = _mm_insert_epi8(v_qid_done, ev_qid2, 10); @@ -3682,19 +3687,30 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port, v_ev_3 = _mm_blend_epi16(v_unpk_ev_23, v_qe_3, 0x0F); v_ev_3 = _mm_alignr_epi8(v_ev_3, v_ev_3, 8); _mm_storeu_si128((__m128i *)&events[3], v_ev_3); + DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched3], + 1); + /* fallthrough */ case 3: v_ev_2 = _mm_unpacklo_epi64(v_unpk_ev_23, v_qe_2); _mm_storeu_si128((__m128i *)&events[2], v_ev_2); + DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched2], + 1); /* fallthrough */ case 2: v_ev_1 = _mm_blend_epi16(v_unpk_ev_01, v_qe_1, 0x0F); v_ev_1 = _mm_alignr_epi8(v_ev_1, v_ev_1, 8); _mm_storeu_si128((__m128i *)&events[1], v_ev_1); + DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched1], + 1); + /* fallthrough */ case 1: v_ev_0 = _mm_unpacklo_epi64(v_unpk_ev_01, v_qe_0); _mm_storeu_si128((__m128i *)&events[0], v_ev_0); + DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched0], + 1); + } } @@ -4421,7 +4437,7 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, dlb2->poll_interval = dlb2_args->poll_interval; dlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta; dlb2->default_depth_thresh = dlb2_args->default_depth_thresh; - dlb2->vector_opts_disabled = dlb2_args->vector_opts_disabled; + dlb2->vector_opts_enabled = dlb2_args->vector_opts_enabled; err = dlb2_iface_open(&dlb2->qm_instance, name); if (err < 0) { @@ -4525,7 +4541,7 @@ dlb2_parse_params(const char *params, DLB2_POLL_INTERVAL_ARG, DLB2_SW_CREDIT_QUANTA_ARG, DLB2_DEPTH_THRESH_ARG, - DLB2_VECTOR_OPTS_DISAB_ARG, + DLB2_VECTOR_OPTS_ENAB_ARG, NULL }; if (params != NULL && params[0] != '\0') { @@ -4640,11 +4656,11 @@ dlb2_parse_params(const char *params, } ret = rte_kvargs_process(kvlist, - DLB2_VECTOR_OPTS_DISAB_ARG, - set_vector_opts_disab, - &dlb2_args->vector_opts_disabled); + DLB2_VECTOR_OPTS_ENAB_ARG, + set_vector_opts_enab, + &dlb2_args->vector_opts_enabled); if (ret != 0) { - DLB2_LOG_ERR("%s: Error parsing vector opts disabled", + DLB2_LOG_ERR("%s: Error parsing vector opts enabled", name); rte_kvargs_free(kvlist); return ret; diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h index 3140764a5..e23702100 100644 --- a/drivers/event/dlb2/dlb2_priv.h +++ b/drivers/event/dlb2/dlb2_priv.h @@ -32,13 +32,12 @@ #define DLB2_MAX_NUM_EVENTS "max_num_events" #define DLB2_NUM_DIR_CREDITS "num_dir_credits" #define DEV_ID_ARG "dev_id" -#define DLB2_DEFER_SCHED_ARG "defer_sched" #define DLB2_QID_DEPTH_THRESH_ARG "qid_depth_thresh" #define DLB2_COS_ARG "cos" #define DLB2_POLL_INTERVAL_ARG "poll_interval" #define DLB2_SW_CREDIT_QUANTA_ARG "sw_credit_quanta" #define DLB2_DEPTH_THRESH_ARG "default_depth_thresh" -#define DLB2_VECTOR_OPTS_DISAB_ARG "vector_opts_disable" +#define DLB2_VECTOR_OPTS_ENAB_ARG "vector_opts_enable" /* Begin HW related defines and structs */ @@ -566,7 +565,7 @@ struct dlb2_eventdev { uint32_t new_event_limit; int max_num_events_override; int num_dir_credits_override; - bool vector_opts_disabled; + bool vector_opts_enabled; volatile enum dlb2_run_state run_state; uint16_t num_dir_queues; /* total num of evdev dir queues requested */ union { @@ -626,7 +625,7 @@ struct dlb2_devargs { int poll_interval; int sw_credit_quanta; int default_depth_thresh; - bool vector_opts_disabled; + bool vector_opts_enabled; }; /* End Eventdev related defines and structs */