From patchwork Wed Apr 21 08:50:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Juraj_Linke=C5=A1?= X-Patchwork-Id: 91940 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9B08A0548; Wed, 21 Apr 2021 10:50:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7D7BD41A0B; Wed, 21 Apr 2021 10:50:34 +0200 (CEST) Received: from lb.pantheon.sk (lb.pantheon.sk [46.229.239.20]) by mails.dpdk.org (Postfix) with ESMTP id 06DEF41A00 for ; Wed, 21 Apr 2021 10:50:30 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by lb.pantheon.sk (Postfix) with ESMTP id 5E956C5F5C; Wed, 21 Apr 2021 10:50:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at siecit.sk Received: from lb.pantheon.sk ([127.0.0.1]) by localhost (lb.pantheon.sk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EWZTLuJg5yB0; Wed, 21 Apr 2021 10:50:27 +0200 (CEST) Received: from service-node1.lab.pantheon.local (unknown [46.229.239.141]) by lb.pantheon.sk (Postfix) with ESMTP id CC997C5F5E; Wed, 21 Apr 2021 10:50:23 +0200 (CEST) From: =?utf-8?q?Juraj_Linke=C5=A1?= To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, aconole@redhat.com, maicolgabriel@hotmail.com Cc: juraj.linkes@pantheon.tech, dev@dpdk.org Date: Wed, 21 Apr 2021 10:50:16 +0200 Message-Id: <1618995020-4775-5-git-send-email-juraj.linkes@pantheon.tech> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618995020-4775-1-git-send-email-juraj.linkes@pantheon.tech> References: <1615988163-17371-1-git-send-email-juraj.linkes@pantheon.tech> <1618995020-4775-1-git-send-email-juraj.linkes@pantheon.tech> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v16 4/8] eal/arm: update CPU flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There are two execution states on armv8 architecture, aarch64 and aarch32. Add PLATFORM_STR for the latter and update RTE_ARCH_* flags according to e9b97392640. Signed-off-by: Juraj Linkeš --- lib/librte_eal/arm/include/rte_cpuflags_32.h | 1 + lib/librte_eal/arm/rte_cpuflags.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/lib/librte_eal/arm/include/rte_cpuflags_32.h b/lib/librte_eal/arm/include/rte_cpuflags_32.h index b5347be1ec..4e254428a2 100644 --- a/lib/librte_eal/arm/include/rte_cpuflags_32.h +++ b/lib/librte_eal/arm/include/rte_cpuflags_32.h @@ -41,6 +41,7 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_SHA2, RTE_CPUFLAG_CRC32, RTE_CPUFLAG_V7L, + RTE_CPUFLAG_V8L, /* The last item */ RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ }; diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c index e3a53bcece..4167a1a302 100644 --- a/lib/librte_eal/arm/rte_cpuflags.c +++ b/lib/librte_eal/arm/rte_cpuflags.c @@ -46,8 +46,12 @@ struct feature_entry { #define FEAT_DEF(name, reg, bit) \ [RTE_CPUFLAG_##name] = {reg, bit, #name}, +#ifdef RTE_ARCH_32 #ifdef RTE_ARCH_ARMv7 #define PLATFORM_STR "v7l" +#elif defined RTE_ARCH_ARMv8_AARCH32 +#define PLATFORM_STR "v8l" +#endif typedef Elf32_auxv_t _Elfx_auxv_t; const struct feature_entry rte_cpu_feature_table[] = { @@ -79,9 +83,10 @@ const struct feature_entry rte_cpu_feature_table[] = { FEAT_DEF(SHA2, REG_HWCAP2, 3) FEAT_DEF(CRC32, REG_HWCAP2, 4) FEAT_DEF(V7L, REG_PLATFORM, 0) + FEAT_DEF(V8L, REG_PLATFORM, 0) }; -#elif defined RTE_ARCH_ARM64 +#elif defined RTE_ARCH_64 #define PLATFORM_STR "aarch64" typedef Elf64_auxv_t _Elfx_auxv_t; @@ -108,7 +113,7 @@ const struct feature_entry rte_cpu_feature_table[] = { FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) FEAT_DEF(SVEBF16, REG_HWCAP2, 12) - FEAT_DEF(AARCH64, REG_PLATFORM, 1) + FEAT_DEF(AARCH64, REG_PLATFORM, 0) }; #endif /* RTE_ARCH */