From patchwork Thu Apr 15 01:49:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 91511 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7F536A0562; Thu, 15 Apr 2021 03:53:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6BEDF161ED0; Thu, 15 Apr 2021 03:51:12 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id ED96D161E4E for ; Thu, 15 Apr 2021 03:50:49 +0200 (CEST) IronPort-SDR: YoBwpH2byBduYfzenSi0KntJpzqNjokKVsVBcS/wcc7Ixya/q4WJK2gD3a3HfyyinSqat7dn67 Q2oIDCI2rBXg== X-IronPort-AV: E=McAfee;i="6200,9189,9954"; a="194881866" X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="194881866" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2021 18:50:48 -0700 IronPort-SDR: Oo8KkBPs0BKUtZE0MaJ58xIxhCeEIparQXOC5xoJiqN5ha53wvUVyb5oKMrLL2MVH+az+vJcGn xrUlL7Ad56rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="382569927" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:47 -0700 From: Timothy McDaniel To: Cc: dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net Date: Wed, 14 Apr 2021 20:49:19 -0500 Message-Id: <1618451359-20693-28-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com> References: <20210316221857.2254-2-timothy.mcdaniel@intel.com> <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com> Subject: [dpdk-dev] [PATCH v4 27/27] event/dlb: move rte config defines to runtime devargs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The new devarg names and their default values are listed below. The defaults have not changed, and none of these parameters are accessed in the fast path. poll_interval=1000 sw_credit_quantai=32 default_depth_thresh=256 Signed-off-by: Timothy McDaniel --- config/rte_config.h | 3 - drivers/event/dlb/dlb2.c | 109 +++++++++++++++++++++++++++++++-- drivers/event/dlb/dlb2_priv.h | 14 +++++ drivers/event/dlb/pf/dlb2_pf.c | 5 +- 4 files changed, 121 insertions(+), 10 deletions(-) diff --git a/config/rte_config.h b/config/rte_config.h index 1aa852cd7..836aca3c2 100644 --- a/config/rte_config.h +++ b/config/rte_config.h @@ -140,9 +140,6 @@ #define RTE_LIBRTE_QEDE_FW "" /* DLB defines */ -#define RTE_LIBRTE_PMD_DLB_POLL_INTERVAL 1000 #undef RTE_LIBRTE_PMD_DLB_QUELL_STATS -#define RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA 32 -#define RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH 256 #endif /* _RTE_CONFIG_H_ */ diff --git a/drivers/event/dlb/dlb2.c b/drivers/event/dlb/dlb2.c index e5def9357..818b1c367 100644 --- a/drivers/event/dlb/dlb2.c +++ b/drivers/event/dlb/dlb2.c @@ -315,6 +315,66 @@ set_cos(const char *key __rte_unused, return 0; } +static int +set_poll_interval(const char *key __rte_unused, + const char *value, + void *opaque) +{ + int *poll_interval = opaque; + int ret; + + if (value == NULL || opaque == NULL) { + DLB2_LOG_ERR("NULL pointer\n"); + return -EINVAL; + } + + ret = dlb2_string_to_int(poll_interval, value); + if (ret < 0) + return ret; + + return 0; +} + +static int +set_sw_credit_quanta(const char *key __rte_unused, + const char *value, + void *opaque) +{ + int *sw_credit_quanta = opaque; + int ret; + + if (value == NULL || opaque == NULL) { + DLB2_LOG_ERR("NULL pointer\n"); + return -EINVAL; + } + + ret = dlb2_string_to_int(sw_credit_quanta, value); + if (ret < 0) + return ret; + + return 0; +} + +static int +set_default_depth_thresh(const char *key __rte_unused, + const char *value, + void *opaque) +{ + int *default_depth_thresh = opaque; + int ret; + + if (value == NULL || opaque == NULL) { + DLB2_LOG_ERR("NULL pointer\n"); + return -EINVAL; + } + + ret = dlb2_string_to_int(default_depth_thresh, value); + if (ret < 0) + return ret; + + return 0; +} + static int set_qid_depth_thresh(const char *key __rte_unused, const char *value, @@ -923,9 +983,9 @@ dlb2_hw_create_ldb_queue(struct dlb2_eventdev *dlb2, } if (ev_queue->depth_threshold == 0) { - cfg.depth_threshold = RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH; + cfg.depth_threshold = dlb2->default_depth_thresh; ev_queue->depth_threshold = - RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH; + dlb2->default_depth_thresh; } else cfg.depth_threshold = ev_queue->depth_threshold; @@ -1617,7 +1677,7 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev, RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL); ev_port->outstanding_releases = 0; ev_port->inflight_credits = 0; - ev_port->credit_update_quanta = RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA; + ev_port->credit_update_quanta = dlb2->sw_credit_quanta; ev_port->dlb2 = dlb2; /* reverse link */ /* Tear down pre-existing port->queue links */ @@ -1712,9 +1772,9 @@ dlb2_hw_create_dir_queue(struct dlb2_eventdev *dlb2, cfg.port_id = qm_port_id; if (ev_queue->depth_threshold == 0) { - cfg.depth_threshold = RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH; + cfg.depth_threshold = dlb2->default_depth_thresh; ev_queue->depth_threshold = - RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH; + dlb2->default_depth_thresh; } else cfg.depth_threshold = ev_queue->depth_threshold; @@ -3065,7 +3125,7 @@ dlb2_dequeue_wait(struct dlb2_eventdev *dlb2, DLB2_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1); } else { - uint64_t poll_interval = RTE_LIBRTE_PMD_DLB_POLL_INTERVAL; + uint64_t poll_interval = dlb2->poll_interval; uint64_t curr_ticks = rte_get_timer_cycles(); uint64_t init_ticks = curr_ticks; @@ -4020,6 +4080,9 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, dlb2->max_num_events_override = dlb2_args->max_num_events; dlb2->num_dir_credits_override = dlb2_args->num_dir_credits_override; dlb2->qm_instance.cos_id = dlb2_args->cos_id; + dlb2->poll_interval = dlb2_args->poll_interval; + dlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta; + dlb2->default_depth_thresh = dlb2_args->default_depth_thresh; err = dlb2_iface_open(&dlb2->qm_instance, name); if (err < 0) { @@ -4120,6 +4183,9 @@ dlb2_parse_params(const char *params, DEV_ID_ARG, DLB2_QID_DEPTH_THRESH_ARG, DLB2_COS_ARG, + DLB2_POLL_INTERVAL_ARG, + DLB2_SW_CREDIT_QUANTA_ARG, + DLB2_DEPTH_THRESH_ARG, NULL }; if (params != NULL && params[0] != '\0') { @@ -4202,6 +4268,37 @@ dlb2_parse_params(const char *params, return ret; } + ret = rte_kvargs_process(kvlist, DLB2_POLL_INTERVAL_ARG, + set_poll_interval, + &dlb2_args->poll_interval); + if (ret != 0) { + DLB2_LOG_ERR("%s: Error parsing poll interval parameter", + name); + rte_kvargs_free(kvlist); + return ret; + } + + ret = rte_kvargs_process(kvlist, + DLB2_SW_CREDIT_QUANTA_ARG, + set_sw_credit_quanta, + &dlb2_args->sw_credit_quanta); + if (ret != 0) { + DLB2_LOG_ERR("%s: Error parsing sw xredit quanta parameter", + name); + rte_kvargs_free(kvlist); + return ret; + } + + ret = rte_kvargs_process(kvlist, DLB2_DEPTH_THRESH_ARG, + set_default_depth_thresh, + &dlb2_args->default_depth_thresh); + if (ret != 0) { + DLB2_LOG_ERR("%s: Error parsing set depth thresh parameter", + name); + rte_kvargs_free(kvlist); + return ret; + } + rte_kvargs_free(kvlist); } } diff --git a/drivers/event/dlb/dlb2_priv.h b/drivers/event/dlb/dlb2_priv.h index f11e08fca..3c540a264 100644 --- a/drivers/event/dlb/dlb2_priv.h +++ b/drivers/event/dlb/dlb2_priv.h @@ -23,6 +23,11 @@ /* common name for all dlb devs (dlb v2.0, dlb v2.5 ...) */ #define EVDEV_DLB2_NAME_PMD dlb_event +/* Default values for command line devargs */ +#define DLB2_POLL_INTERVAL_DEFAULT 1000 +#define DLB2_SW_CREDIT_QUANTA_DEFAULT 32 +#define DLB2_DEPTH_THRESH_DEFAULT 256 + /* command line arg strings */ #define NUMA_NODE_ARG "numa_node" #define DLB2_MAX_NUM_EVENTS "max_num_events" @@ -31,6 +36,9 @@ #define DLB2_DEFER_SCHED_ARG "defer_sched" #define DLB2_QID_DEPTH_THRESH_ARG "qid_depth_thresh" #define DLB2_COS_ARG "cos" +#define DLB2_POLL_INTERVAL_ARG "poll_interval" +#define DLB2_SW_CREDIT_QUANTA_ARG "sw_credit_quanta" +#define DLB2_DEPTH_THRESH_ARG "default_depth_thresh" /* Begin HW related defines and structs */ @@ -571,6 +579,9 @@ struct dlb2_eventdev { bool global_dequeue_wait; /* Not using per dequeue wait if true */ bool defer_sched; enum dlb2_cq_poll_modes poll_mode; + int poll_interval; + int sw_credit_quanta; + int default_depth_thresh; uint8_t revision; uint8_t version; bool configured; @@ -604,6 +615,9 @@ struct dlb2_devargs { int defer_sched; struct dlb2_qid_depth_thresholds qid_depth_thresholds; enum dlb2_cos cos_id; + int poll_interval; + int sw_credit_quanta; + int default_depth_thresh; }; /* End Eventdev related defines and structs */ diff --git a/drivers/event/dlb/pf/dlb2_pf.c b/drivers/event/dlb/pf/dlb2_pf.c index f57dc1584..e9da89d65 100644 --- a/drivers/event/dlb/pf/dlb2_pf.c +++ b/drivers/event/dlb/pf/dlb2_pf.c @@ -615,7 +615,10 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev) .max_num_events = DLB2_MAX_NUM_LDB_CREDITS, .num_dir_credits_override = -1, .qid_depth_thresholds = { {0} }, - .cos_id = DLB2_COS_DEFAULT + .cos_id = DLB2_COS_DEFAULT, + .poll_interval = DLB2_POLL_INTERVAL_DEFAULT, + .sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT, + .default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT }; struct dlb2_eventdev *dlb2;