From patchwork Tue Apr 13 20:14:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 91302 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9F78EA0524; Tue, 13 Apr 2021 22:16:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0F4F01612DB; Tue, 13 Apr 2021 22:16:20 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 2DA401612C3 for ; Tue, 13 Apr 2021 22:16:13 +0200 (CEST) IronPort-SDR: kMysBeL577g9go1seZg0lRCAyWq+WjEpCL4oOrae/hSJ3a9hEU07iOU8p5gdyg9SF/bjyn2uQ4 wkYOeT9VUi5w== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="194519690" X-IronPort-AV: E=Sophos;i="5.82,220,1613462400"; d="scan'208";a="194519690" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 13:16:11 -0700 IronPort-SDR: Ya9nUTpzGdmeXMLxZueW1mlS9qUVXV3Gdm5IaSwQ65ltlgjvwe4p2tV5wWmJeRHFgBhxHQ/sDL mPTWzhdv8q0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,220,1613462400"; d="scan'208";a="424406473" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by orsmga008.jf.intel.com with ESMTP; 13 Apr 2021 13:16:10 -0700 From: Timothy McDaniel To: Cc: dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com, harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net Date: Tue, 13 Apr 2021 15:14:34 -0500 Message-Id: <1618344896-2090-5-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com> References: <20210316221857.2254-2-timothy.mcdaniel@intel.com> <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com> Subject: [dpdk-dev] [PATCH v3 04/26] event/dlb2: add v2.5 get resources X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" DLB v2.5 uses a new credit scheme, where directed and load balanced credits are unified, instead of having separate directed and load balanced credit pools. Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2.c | 20 ++++-- drivers/event/dlb2/dlb2_user.h | 14 +++- drivers/event/dlb2/pf/base/dlb2_resource.c | 48 -------------- .../event/dlb2/pf/base/dlb2_resource_new.c | 66 +++++++++++++++++++ 4 files changed, 92 insertions(+), 56 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 7f5b9141b..0048f6a1b 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -132,17 +132,25 @@ dlb2_hw_query_resources(struct dlb2_eventdev *dlb2) evdev_dlb2_default_info.max_event_ports = dlb2->hw_rsrc_query_results.num_ldb_ports; - evdev_dlb2_default_info.max_num_events = - dlb2->hw_rsrc_query_results.num_ldb_credits; - + if (dlb2->version == DLB2_HW_V2_5) { + evdev_dlb2_default_info.max_num_events = + dlb2->hw_rsrc_query_results.num_credits; + } else { + evdev_dlb2_default_info.max_num_events = + dlb2->hw_rsrc_query_results.num_ldb_credits; + } /* Save off values used when creating the scheduling domain. */ handle->info.num_sched_domains = dlb2->hw_rsrc_query_results.num_sched_domains; - handle->info.hw_rsrc_max.nb_events_limit = - dlb2->hw_rsrc_query_results.num_ldb_credits; - + if (dlb2->version == DLB2_HW_V2_5) { + handle->info.hw_rsrc_max.nb_events_limit = + dlb2->hw_rsrc_query_results.num_credits; + } else { + handle->info.hw_rsrc_max.nb_events_limit = + dlb2->hw_rsrc_query_results.num_ldb_credits; + } handle->info.hw_rsrc_max.num_queues = dlb2->hw_rsrc_query_results.num_ldb_queues + dlb2->hw_rsrc_query_results.num_dir_ports; diff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb2/dlb2_user.h index f4bda7822..b7d125dec 100644 --- a/drivers/event/dlb2/dlb2_user.h +++ b/drivers/event/dlb2/dlb2_user.h @@ -195,9 +195,12 @@ struct dlb2_create_sched_domain_args { * contiguous range of history list entries. * - num_ldb_credits: Amount of available load-balanced QE storage. * - num_dir_credits: Amount of available directed QE storage. + * - response.status: Detailed error code. In certain cases, such as if the + * ioctl request arg is invalid, the driver won't set status. */ struct dlb2_get_num_resources_args { /* Output parameters */ + struct dlb2_cmd_response response; __u32 num_sched_domains; __u32 num_ldb_queues; __u32 num_ldb_ports; @@ -206,8 +209,15 @@ struct dlb2_get_num_resources_args { __u32 num_atomic_inflights; __u32 num_hist_list_entries; __u32 max_contiguous_hist_list_entries; - __u32 num_ldb_credits; - __u32 num_dir_credits; + union { + struct { + __u32 num_ldb_credits; + __u32 num_dir_credits; + }; + struct { + __u32 num_credits; + }; + }; }; /* diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c index 7ba6521ef..eda983d85 100644 --- a/drivers/event/dlb2/pf/base/dlb2_resource.c +++ b/drivers/event/dlb2/pf/base/dlb2_resource.c @@ -58,54 +58,6 @@ void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw) DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val); } -int dlb2_hw_get_num_resources(struct dlb2_hw *hw, - struct dlb2_get_num_resources_args *arg, - bool vdev_req, - unsigned int vdev_id) -{ - struct dlb2_function_resources *rsrcs; - struct dlb2_bitmap *map; - int i; - - if (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS) - return -EINVAL; - - if (vdev_req) - rsrcs = &hw->vdev[vdev_id]; - else - rsrcs = &hw->pf; - - arg->num_sched_domains = rsrcs->num_avail_domains; - - arg->num_ldb_queues = rsrcs->num_avail_ldb_queues; - - arg->num_ldb_ports = 0; - for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) - arg->num_ldb_ports += rsrcs->num_avail_ldb_ports[i]; - - arg->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0]; - arg->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1]; - arg->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2]; - arg->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3]; - - arg->num_dir_ports = rsrcs->num_avail_dir_pq_pairs; - - arg->num_atomic_inflights = rsrcs->num_avail_aqed_entries; - - map = rsrcs->avail_hist_list_entries; - - arg->num_hist_list_entries = dlb2_bitmap_count(map); - - arg->max_contiguous_hist_list_entries = - dlb2_bitmap_longest_set_range(map); - - arg->num_ldb_credits = rsrcs->num_avail_qed_entries; - - arg->num_dir_credits = rsrcs->num_avail_dqed_entries; - - return 0; -} - void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw) { union dlb2_chp_cfg_chp_csr_ctrl r0; diff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c index 175b0799e..14b97dbf9 100644 --- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c +++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c @@ -257,3 +257,69 @@ void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw, enum dlb2_hw_ver ver) DLB2_CSR_WR(hw, DLB2_CM_CFG_PM_PMCSR_DISABLE(ver), pmcsr_dis); } +/** + * dlb2_hw_get_num_resources() - query the PCI function's available resources + * @hw: dlb2_hw handle for a particular device. + * @arg: pointer to resource counts. + * @vdev_req: indicates whether this request came from a vdev. + * @vdev_id: If vdev_req is true, this contains the vdev's ID. + * + * This function returns the number of available resources for the PF or for a + * VF. + * + * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual + * device. + * + * Return: + * Returns 0 upon success, -EINVAL if vdev_req is true and vdev_id is + * invalid. + */ +int dlb2_hw_get_num_resources(struct dlb2_hw *hw, + struct dlb2_get_num_resources_args *arg, + bool vdev_req, + unsigned int vdev_id) +{ + struct dlb2_function_resources *rsrcs; + struct dlb2_bitmap *map; + int i; + + if (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS) + return -EINVAL; + + if (vdev_req) + rsrcs = &hw->vdev[vdev_id]; + else + rsrcs = &hw->pf; + + arg->num_sched_domains = rsrcs->num_avail_domains; + + arg->num_ldb_queues = rsrcs->num_avail_ldb_queues; + + arg->num_ldb_ports = 0; + for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) + arg->num_ldb_ports += rsrcs->num_avail_ldb_ports[i]; + + arg->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0]; + arg->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1]; + arg->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2]; + arg->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3]; + + arg->num_dir_ports = rsrcs->num_avail_dir_pq_pairs; + + arg->num_atomic_inflights = rsrcs->num_avail_aqed_entries; + + map = rsrcs->avail_hist_list_entries; + + arg->num_hist_list_entries = dlb2_bitmap_count(map); + + arg->max_contiguous_hist_list_entries = + dlb2_bitmap_longest_set_range(map); + + if (hw->ver == DLB2_HW_V2) { + arg->num_ldb_credits = rsrcs->num_avail_qed_entries; + arg->num_dir_credits = rsrcs->num_avail_dqed_entries; + } else { + arg->num_credits = rsrcs->num_avail_entries; + } + return 0; +}