From patchwork Wed Jan 20 11:29:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 86968 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7360FA0A05; Wed, 20 Jan 2021 12:35:00 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC2EE140D01; Wed, 20 Jan 2021 12:34:58 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 090CF140CF8 for ; Wed, 20 Jan 2021 12:34:57 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from matan@nvidia.com) with SMTP; 20 Jan 2021 13:34:57 +0200 Received: from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx [10.210.16.10]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10KBTfXH001381; Wed, 20 Jan 2021 13:34:57 +0200 From: Matan Azrad To: dev@dpdk.org Cc: Thomas Monjalon , Ashish Gupta , Fiona Trahe , akhil.goyal@nxp.com Date: Wed, 20 Jan 2021 11:29:34 +0000 Message-Id: <1611142175-409485-11-git-send-email-matan@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1611142175-409485-1-git-send-email-matan@nvidia.com> References: <1610554690-411627-1-git-send-email-matan@nvidia.com> <1611142175-409485-1-git-send-email-matan@nvidia.com> Subject: [dpdk-dev] [PATCH v3 10/11] compress/mlx5: support 32-bit systems X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In order to support 32-bit systems, the 8B doorbell write should be done by 2 4B stores. The order between the store is important, that's why memory barrier should be used between them. The doorbell address is shared between all the queues, that's why a lock should wrap the 2 stores. Signed-off-by: Matan Azrad Acked-by: Viacheslav Ovsiienko --- drivers/compress/mlx5/mlx5_compress.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 7a43d9e..f7ef913 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -50,6 +50,10 @@ struct mlx5_compress_priv { LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; rte_spinlock_t xform_sl; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ + volatile uint64_t *uar_addr; +#ifndef RTE_ARCH_64 + rte_spinlock_t uar32_sl; +#endif /* RTE_ARCH_64 */ }; struct mlx5_compress_qp { @@ -57,7 +61,6 @@ struct mlx5_compress_qp { uint16_t entries_n; uint16_t pi; uint16_t ci; - volatile uint64_t *uar_addr; struct mlx5_mr_ctrl mr_ctrl; int socket_id; struct mlx5_devx_cq cq; @@ -208,8 +211,6 @@ struct mlx5_compress_qp { qp->priv = priv; qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), RTE_CACHE_LINE_SIZE); - qp->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); - MLX5_ASSERT(qp->uar_addr); if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n * sizeof(struct mlx5_gga_compress_opaque), &qp->opaque_mr) != 0) { @@ -423,6 +424,24 @@ struct mlx5_compress_qp { return dseg->lkey; } +/* + * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and + * 64bit architectures. + */ +static __rte_always_inline void +mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv) +{ +#ifdef RTE_ARCH_64 + *priv->uar_addr = val; +#else /* !RTE_ARCH_64 */ + rte_spinlock_lock(&priv->uar32_sl); + *(volatile uint32_t *)priv->uar_addr = val; + rte_io_wmb(); + *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; + rte_spinlock_unlock(&priv->uar32_sl); +#endif +} + static uint16_t mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, uint16_t nb_ops) @@ -486,7 +505,7 @@ struct mlx5_compress_qp { rte_io_wmb(); qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); rte_wmb(); - *qp->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/ + mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv); rte_wmb(); return nb_ops; } @@ -692,6 +711,11 @@ struct mlx5_compress_qp { DRV_LOG(ERR, "Failed to allocate UAR."); return -1; } + priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); + MLX5_ASSERT(qp->uar_addr); +#ifndef RTE_ARCH_64 + rte_spinlock_init(&priv->uar32_sl); +#endif /* RTE_ARCH_64 */ return 0; }