From patchwork Mon Jan 11 13:59:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 86283 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 401BCA09FF; Mon, 11 Jan 2021 14:59:34 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A2D2140CEE; Mon, 11 Jan 2021 14:59:34 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 1CE8C140CD7 for ; Mon, 11 Jan 2021 14:59:32 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from matan@nvidia.com) with SMTP; 11 Jan 2021 15:59:29 +0200 Received: from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx [10.210.16.10]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BDxPKI010436; Mon, 11 Jan 2021 15:59:29 +0200 From: Matan Azrad To: dev@dpdk.org Cc: Thomas Monjalon , Ashish Gupta , Fiona Trahe Date: Mon, 11 Jan 2021 13:59:11 +0000 Message-Id: <1610373560-253158-2-git-send-email-matan@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1610373560-253158-1-git-send-email-matan@nvidia.com> References: <1610373560-253158-1-git-send-email-matan@nvidia.com> Subject: [dpdk-dev] [PATCH 01/10] common/mlx5: add DevX attributes for compress X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add the DevX attributes for compress related engiens: compress decompress dma Signed-off-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 10 ++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 7 +++++++ drivers/common/mlx5/mlx5_prm.h | 18 ++++++++++++++++-- 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 790a701..84a835d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -725,6 +725,16 @@ struct mlx5_devx_obj * attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); + attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); + attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); + attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); + attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, + compress_min_block_size); + attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); + attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, + log_compress_mmo_size); + attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, + log_decompress_mmo_size); if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index a14f3bf..a279422 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -127,6 +127,13 @@ struct mlx5_hca_attr { uint32_t log_max_srq; uint32_t log_max_srq_sz; uint32_t rss_ind_tbl_cap; + uint32_t mmo_dma_en:1; + uint32_t mmo_compress_en:1; + uint32_t mmo_decompress_en:1; + uint32_t compress_min_block_size:4; + uint32_t log_max_mmo_dma:5; + uint32_t log_max_mmo_compress:5; + uint32_t log_max_mmo_decompress:5; }; struct mlx5_devx_wq_attr { diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 8c9b53c..6f5a6cf 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1120,7 +1120,15 @@ enum { struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_0[0x30]; u8 vhca_id[0x10]; - u8 reserved_at_40[0x40]; + u8 reserved_at_40[0x20]; + u8 reserved_at_60[0x3]; + u8 log_regexp_scatter_gather_size[0x5]; + u8 reserved_at_68[0x3]; + u8 log_dma_mmo_size[5]; + u8 reserved_at_70[0x3]; + u8 log_compress_mmo_size[5]; + u8 reserved_at_78[0x3]; + u8 log_decompress_mmo_size[5]; u8 log_max_srq_sz[0x8]; u8 log_max_qp_sz[0x8]; u8 reserved_at_90[0x9]; @@ -1168,7 +1176,13 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_max_ra_res_dc[0x6]; u8 reserved_at_140[0xa]; u8 log_max_ra_req_qp[0x6]; - u8 reserved_at_150[0xa]; + u8 rtr2rts_qp_counters_set_id[1]; + u8 rts2rts_udp_sport[1]; + u8 rts2rts_lag_tx_port_affinity[1]; + u8 dma_mmo[1]; + u8 compress_min_block_size[4]; + u8 compress[1]; + u8 decompress[1]; u8 log_max_ra_res_qp[0x6]; u8 end_pad[0x1]; u8 cc_query_allowed[0x1];