diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index 4f52ed0..f58f4f7 100644
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -198,7 +198,6 @@ hns3_cmd_csq_clean(struct hns3_hw *hw)
 	int clean;
 
 	head = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG);
-
 	if (!is_valid_csq_clean_head(csq, head)) {
 		hns3_err(hw, "wrong cmd head (%u, %u-%u)", head,
 			    csq->next_to_use, csq->next_to_clean);
diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index ba96724..b27cf67 100644
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -238,7 +238,6 @@ hns3_interrupt_handler(void *param)
 	hns3_pf_disable_irq0(hw);
 
 	event_cause = hns3_check_event_cause(hns, &clearval);
-
 	/* vector 0 interrupt is shared with reset and mailbox source events. */
 	if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 		hns3_warn(hw, "Received err interrupt");
@@ -3556,9 +3555,7 @@ hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
 	for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
 		priv = &buf_alloc->priv_buf[i];
 		mask = BIT((uint8_t)i);
-
-		if (hw->hw_tc_map & mask &&
-		    hw->dcb_info.hw_pfc_map & mask) {
+		if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
 			/* Reduce the number of pfc TC with private buffer */
 			priv->wl.low = 0;
 			priv->enable = 0;
@@ -3612,7 +3609,6 @@ hns3_only_alloc_priv_buff(struct hns3_hw *hw,
 
 	for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 		priv = &buf_alloc->priv_buf[i];
-
 		priv->enable = 0;
 		priv->wl.low = 0;
 		priv->wl.high = 0;
diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index 63e0c2f..7470de0 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -831,7 +831,6 @@ struct hns3_adapter {
 
 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
 #define rounddown(x, y) ((x) - ((x) % (y)))
-
 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 
 /*
diff --git a/drivers/net/hns3/hns3_flow.c b/drivers/net/hns3/hns3_flow.c
index 2fff157..ee6ec15 100644
--- a/drivers/net/hns3/hns3_flow.c
+++ b/drivers/net/hns3/hns3_flow.c
@@ -209,8 +209,7 @@ hns3_counter_query(struct rte_eth_dev *dev, struct rte_flow *flow,
 
 	ret = hns3_get_count(&hns->hw, flow->counter_id, &value);
 	if (ret) {
-		rte_flow_error_set(error, -ret,
-				   RTE_FLOW_ERROR_TYPE_HANDLE,
+		rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_HANDLE,
 				   NULL, "Read counter fail.");
 		return ret;
 	}
@@ -547,7 +546,6 @@ hns3_parse_ipv4(const struct rte_flow_item *item, struct hns3_fdir_rule *rule,
 
 	if (item->mask) {
 		ipv4_mask = item->mask;
-
 		if (ipv4_mask->hdr.total_length ||
 		    ipv4_mask->hdr.packet_id ||
 		    ipv4_mask->hdr.fragment_offset ||
@@ -616,8 +614,8 @@ hns3_parse_ipv6(const struct rte_flow_item *item, struct hns3_fdir_rule *rule,
 
 	if (item->mask) {
 		ipv6_mask = item->mask;
-		if (ipv6_mask->hdr.vtc_flow ||
-		    ipv6_mask->hdr.payload_len || ipv6_mask->hdr.hop_limits) {
+		if (ipv6_mask->hdr.vtc_flow || ipv6_mask->hdr.payload_len ||
+		    ipv6_mask->hdr.hop_limits) {
 			return rte_flow_error_set(error, EINVAL,
 						  RTE_FLOW_ERROR_TYPE_ITEM_MASK,
 						  item,
@@ -672,12 +670,10 @@ hns3_parse_tcp(const struct rte_flow_item *item, struct hns3_fdir_rule *rule,
 
 	if (item->mask) {
 		tcp_mask = item->mask;
-		if (tcp_mask->hdr.sent_seq ||
-		    tcp_mask->hdr.recv_ack ||
-		    tcp_mask->hdr.data_off ||
-		    tcp_mask->hdr.tcp_flags ||
-		    tcp_mask->hdr.rx_win ||
-		    tcp_mask->hdr.cksum || tcp_mask->hdr.tcp_urp) {
+		if (tcp_mask->hdr.sent_seq || tcp_mask->hdr.recv_ack ||
+		    tcp_mask->hdr.data_off || tcp_mask->hdr.tcp_flags ||
+		    tcp_mask->hdr.rx_win || tcp_mask->hdr.cksum ||
+		    tcp_mask->hdr.tcp_urp) {
 			return rte_flow_error_set(error, EINVAL,
 						  RTE_FLOW_ERROR_TYPE_ITEM_MASK,
 						  item,
@@ -776,7 +772,6 @@ hns3_parse_sctp(const struct rte_flow_item *item, struct hns3_fdir_rule *rule,
 						  RTE_FLOW_ERROR_TYPE_ITEM_MASK,
 						  item,
 						  "Only support src & dst port in SCTP");
-
 		if (sctp_mask->hdr.src_port) {
 			hns3_set_bit(rule->input_set, INNER_SRC_PORT, 1);
 			rule->key_conf.mask.src_port =
@@ -1069,8 +1064,7 @@ hns3_parse_tunnel(const struct rte_flow_item *item, struct hns3_fdir_rule *rule,
 }
 
 static int
-hns3_parse_normal(const struct rte_flow_item *item,
-		  struct hns3_fdir_rule *rule,
+hns3_parse_normal(const struct rte_flow_item *item, struct hns3_fdir_rule *rule,
 		  struct items_step_mngr *step_mngr,
 		  struct rte_flow_error *error)
 {
@@ -1331,9 +1325,8 @@ hns3_rss_conf_copy(struct hns3_rss_conf *out,
 		.key_len = in->key_len,
 		.queue_num = in->queue_num,
 	};
-	out->conf.queue =
-		memcpy(out->queue, in->queue,
-		       sizeof(*in->queue) * in->queue_num);
+	out->conf.queue = memcpy(out->queue, in->queue,
+				sizeof(*in->queue) * in->queue_num);
 	if (in->key)
 		out->conf.key = memcpy(out->key, in->key, in->key_len);
 
@@ -1783,17 +1776,15 @@ hns3_flow_create(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 
 	flow = rte_zmalloc("hns3 flow", sizeof(struct rte_flow), 0);
 	if (flow == NULL) {
-		rte_flow_error_set(error, ENOMEM,
-				   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
-				   "Failed to allocate flow memory");
+		rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
+				   NULL, "Failed to allocate flow memory");
 		return NULL;
 	}
 	flow_node = rte_zmalloc("hns3 flow node",
 				sizeof(struct hns3_flow_mem), 0);
 	if (flow_node == NULL) {
-		rte_flow_error_set(error, ENOMEM,
-				   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
-				   "Failed to allocate flow list memory");
+		rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
+				   NULL, "Failed to allocate flow list memory");
 		rte_free(flow);
 		return NULL;
 	}
diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c
index bfd2ba8..02e221a 100644
--- a/drivers/net/hns3/hns3_intr.c
+++ b/drivers/net/hns3/hns3_intr.c
@@ -28,201 +28,281 @@ static const char *reset_string[HNS3_MAX_RESET] = {
 };
 
 static const struct hns3_hw_error mac_afifo_tnl_int[] = {
-	{ .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
+	{ .int_msk = BIT(0),
+	  .msg = "egu_cge_afifo_ecc_1bit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "egu_cge_afifo_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
+	{ .int_msk = BIT(2),
+	  .msg = "egu_lge_afifo_ecc_1bit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
+	{ .int_msk = BIT(3),
+	  .msg = "egu_lge_afifo_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
+	{ .int_msk = BIT(4),
+	  .msg = "cge_igu_afifo_ecc_1bit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
+	{ .int_msk = BIT(5),
+	  .msg = "cge_igu_afifo_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
+	{ .int_msk = BIT(6),
+	  .msg = "lge_igu_afifo_ecc_1bit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
+	{ .int_msk = BIT(7),
+	  .msg = "lge_igu_afifo_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
+	{ .int_msk = BIT(8),
+	  .msg = "cge_igu_afifo_overflow_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
+	{ .int_msk = BIT(9),
+	  .msg = "lge_igu_afifo_overflow_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
+	{ .int_msk = BIT(10),
+	  .msg = "egu_cge_afifo_underrun_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
+	{ .int_msk = BIT(11),
+	  .msg = "egu_lge_afifo_underrun_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
+	{ .int_msk = BIT(12),
+	  .msg = "egu_ge_afifo_underrun_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
+	{ .int_msk = BIT(13),
+	  .msg = "ge_igu_afifo_overflow_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {
-	{ .int_msk = 0xFFFFFFFF, .msg = "rpu_rx_pkt_ecc_mbit_err",
+	{ .int_msk = 0xFFFFFFFF,
+	  .msg = "rpu_rx_pkt_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = {
-	{ .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
+	{ .int_msk = BIT(13),
+	  .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
+	{ .int_msk = BIT(14),
+	  .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
+	{ .int_msk = BIT(15),
+	  .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
+	{ .int_msk = BIT(16),
+	  .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
+	{ .int_msk = BIT(17),
+	  .msg = "rcb_tx_ring_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
+	{ .int_msk = BIT(18),
+	  .msg = "rcb_rx_ring_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
+	{ .int_msk = BIT(19),
+	  .msg = "rcb_tx_fbd_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
+	{ .int_msk = BIT(20),
+	  .msg = "rcb_rx_ebd_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
+	{ .int_msk = BIT(21),
+	  .msg = "rcb_tso_info_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
+	{ .int_msk = BIT(22),
+	  .msg = "rcb_tx_int_info_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
+	{ .int_msk = BIT(23),
+	  .msg = "rcb_rx_int_info_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
+	{ .int_msk = BIT(24),
+	  .msg = "tpu_tx_pkt_0_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
+	{ .int_msk = BIT(25),
+	  .msg = "tpu_tx_pkt_1_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(26), .msg = "rd_bus_err",
+	{ .int_msk = BIT(26),
+	  .msg = "rd_bus_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(27), .msg = "wr_bus_err",
+	{ .int_msk = BIT(27),
+	  .msg = "wr_bus_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
+	{ .int_msk = BIT(30),
+	  .msg = "ooo_ecc_err_detect",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
+	{ .int_msk = BIT(31),
+	  .msg = "ooo_ecc_err_multpl",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = {
-	{ .int_msk = BIT(29), .msg = "rx_q_search_miss",
+	{ .int_msk = BIT(29),
+	  .msg = "rx_q_search_miss",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ssu_port_based_pf_int[] = {
-	{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
+	{ .int_msk = BIT(0),
+	  .msg = "roc_pkt_without_key_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "low_water_line_err_port",
+	{ .int_msk = BIT(9),
+	  .msg = "low_water_line_err_port",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppp_pf_abnormal_int[] = {
-	{ .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
+	{ .int_msk = BIT(0),
+	  .msg = "tx_vlan_tag_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
+	{ .int_msk = BIT(1),
+	  .msg = "rss_list_tc_unassigned_queue_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = {
-	{ .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
+	{ .int_msk = BIT(3),
+	  .msg = "tx_rd_fbd_poison",
 	  .reset_level = HNS3_FUNC_RESET },
-	{ .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
+	{ .int_msk = BIT(4),
+	  .msg = "rx_rd_ebd_poison",
 	  .reset_level = HNS3_FUNC_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = {
-	{ .int_msk = BIT(0), .msg = "over_8bd_no_fe",
+	{ .int_msk = BIT(0),
+	  .msg = "over_8bd_no_fe",
 	  .reset_level = HNS3_FUNC_RESET },
-	{ .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
+	{ .int_msk = BIT(1),
+	  .msg = "tso_mss_cmp_min_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
+	{ .int_msk = BIT(2),
+	  .msg = "tso_mss_cmp_max_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(5), .msg = "buf_wait_timeout",
+	{ .int_msk = BIT(5),
+	  .msg = "buf_wait_timeout",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error imp_tcm_ecc_int[] = {
-	{ .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "imp_itcm0_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err",
+	{ .int_msk = BIT(3),
+	  .msg = "imp_itcm1_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err",
+	{ .int_msk = BIT(5),
+	  .msg = "imp_itcm2_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err",
+	{ .int_msk = BIT(7),
+	  .msg = "imp_itcm3_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err",
+	{ .int_msk = BIT(9),
+	  .msg = "imp_dtcm0_mem0_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err",
+	{ .int_msk = BIT(11),
+	  .msg = "imp_dtcm0_mem1_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err",
+	{ .int_msk = BIT(13),
+	  .msg = "imp_dtcm1_mem0_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err",
+	{ .int_msk = BIT(15),
+	  .msg = "imp_dtcm1_mem1_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err",
+	{ .int_msk = BIT(17),
+	  .msg = "imp_itcm4_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error cmdq_mem_ecc_int[] = {
-	{ .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
+	{ .int_msk = BIT(3),
+	  .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
+	{ .int_msk = BIT(5),
+	  .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
+	{ .int_msk = BIT(7),
+	  .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err",
+	{ .int_msk = BIT(9),
+	  .msg = "cmdq_nic_rx_head_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err",
+	{ .int_msk = BIT(11),
+	  .msg = "cmdq_nic_tx_head_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
+	{ .int_msk = BIT(13),
+	  .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
+	{ .int_msk = BIT(15),
+	  .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error tqp_int_ecc_int[] = {
-	{ .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err",
+	{ .int_msk = BIT(6),
+	  .msg = "tqp_int_cfg_even_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err",
+	{ .int_msk = BIT(7),
+	  .msg = "tqp_int_cfg_odd_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err",
+	{ .int_msk = BIT(8),
+	  .msg = "tqp_int_ctrl_even_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
+	{ .int_msk = BIT(9),
+	  .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err",
+	{ .int_msk = BIT(10),
+	  .msg = "tx_que_scan_int_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err",
+	{ .int_msk = BIT(11),
+	  .msg = "rx_que_scan_int_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error imp_rd_poison_int[] = {
-	{ .int_msk = BIT(0), .msg = "imp_rd_poison_int",
+	{ .int_msk = BIT(0),
+	  .msg = "imp_rd_poison_int",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 #define HNS3_SSU_MEM_ECC_ERR(x) \
-	{ .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \
+	{ .int_msk = BIT(x), \
+	  .msg = "ssu_mem" #x "_ecc_mbit_err", \
 	  .reset_level = HNS3_GLOBAL_RESET }
 
 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {
@@ -258,515 +338,726 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {
 	HNS3_SSU_MEM_ECC_ERR(29),
 	HNS3_SSU_MEM_ECC_ERR(30),
 	HNS3_SSU_MEM_ECC_ERR(31),
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {
-	{ .int_msk = BIT(0), .msg = "ssu_mem32_ecc_mbit_err",
+	{ .int_msk = BIT(0),
+	  .msg = "ssu_mem32_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ssu_common_ecc_int[] = {
-	{ .int_msk = BIT(0), .msg = "buf_sum_err",
+	{ .int_msk = BIT(0),
+	  .msg = "buf_sum_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(1), .msg = "ppp_mb_num_err",
+	{ .int_msk = BIT(1),
+	  .msg = "ppp_mb_num_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = BIT(2), .msg = "ppp_mbid_err",
+	{ .int_msk = BIT(2),
+	  .msg = "ppp_mbid_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "ppp_rlt_mac_err",
+	{ .int_msk = BIT(3),
+	  .msg = "ppp_rlt_mac_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "ppp_rlt_host_err",
+	{ .int_msk = BIT(4),
+	  .msg = "ppp_rlt_host_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "cks_edit_position_err",
+	{ .int_msk = BIT(5),
+	  .msg = "cks_edit_position_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "cks_edit_condition_err",
+	{ .int_msk = BIT(6),
+	  .msg = "cks_edit_condition_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "vlan_edit_condition_err",
+	{ .int_msk = BIT(7),
+	  .msg = "vlan_edit_condition_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(8), .msg = "vlan_num_ot_err",
+	{ .int_msk = BIT(8),
+	  .msg = "vlan_num_ot_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "vlan_num_in_err",
+	{ .int_msk = BIT(9),
+	  .msg = "vlan_num_in_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error igu_int[] = {
-	{ .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err",
+	{ .int_msk = BIT(0),
+	  .msg = "igu_rx_buf0_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err",
+	{ .int_msk = BIT(2),
+	  .msg = "igu_rx_buf1_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error msix_ecc_int[] = {
-	{ .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "msix_nic_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {
-	{ .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err",
+	{ .int_msk = BIT(0),
+	  .msg = "vf_vlan_ad_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "umv_mcast_group_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err",
+	{ .int_msk = BIT(2),
+	  .msg = "umv_key_mem0_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err",
+	{ .int_msk = BIT(3),
+	  .msg = "umv_key_mem1_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err",
+	{ .int_msk = BIT(4),
+	  .msg = "umv_key_mem2_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err",
+	{ .int_msk = BIT(5),
+	  .msg = "umv_key_mem3_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err",
+	{ .int_msk = BIT(6),
+	  .msg = "umv_ad_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err",
+	{ .int_msk = BIT(7),
+	  .msg = "rss_tc_mode_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err",
+	{ .int_msk = BIT(8),
+	  .msg = "rss_idt_mem0_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err",
+	{ .int_msk = BIT(9),
+	  .msg = "rss_idt_mem1_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err",
+	{ .int_msk = BIT(10),
+	  .msg = "rss_idt_mem2_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err",
+	{ .int_msk = BIT(11),
+	  .msg = "rss_idt_mem3_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err",
+	{ .int_msk = BIT(12),
+	  .msg = "rss_idt_mem4_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err",
+	{ .int_msk = BIT(13),
+	  .msg = "rss_idt_mem5_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err",
+	{ .int_msk = BIT(14),
+	  .msg = "rss_idt_mem6_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err",
+	{ .int_msk = BIT(15),
+	  .msg = "rss_idt_mem7_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err",
+	{ .int_msk = BIT(16),
+	  .msg = "rss_idt_mem8_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err",
+	{ .int_msk = BIT(17),
+	  .msg = "rss_idt_mem9_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err",
+	{ .int_msk = BIT(18),
+	  .msg = "rss_idt_mem10_ecc_m1bit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err",
+	{ .int_msk = BIT(19),
+	  .msg = "rss_idt_mem11_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err",
+	{ .int_msk = BIT(20),
+	  .msg = "rss_idt_mem12_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err",
+	{ .int_msk = BIT(21),
+	  .msg = "rss_idt_mem13_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err",
+	{ .int_msk = BIT(22),
+	  .msg = "rss_idt_mem14_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err",
+	{ .int_msk = BIT(23),
+	  .msg = "rss_idt_mem15_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err",
+	{ .int_msk = BIT(24),
+	  .msg = "port_vlan_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err",
+	{ .int_msk = BIT(25),
+	  .msg = "mcast_linear_table_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err",
+	{ .int_msk = BIT(26),
+	  .msg = "mcast_result_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err",
+	{ .int_msk = BIT(27),
+	  .msg = "flow_director_ad_mem0_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err",
+	{ .int_msk = BIT(28),
+	  .msg = "flow_director_ad_mem1_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err",
+	{ .int_msk = BIT(29),
+	  .msg = "rx_vlan_tag_memory_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
+	{ .int_msk = BIT(30),
+	  .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {
-	{ .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err",
+	{ .int_msk = BIT(0),
+	  .msg = "hfs_fifo_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err",
+	{ .int_msk = BIT(2),
+	  .msg = "tx_vlan_tag_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err",
+	{ .int_msk = BIT(3),
+	  .msg = "FD_CN0_memory_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err",
+	{ .int_msk = BIT(4),
+	  .msg = "FD_CN1_memory_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err",
+	{ .int_msk = BIT(5),
+	  .msg = "GRO_AD_memory_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {
-	{ .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err",
+	{ .int_msk = BIT(4),
+	  .msg = "gro_bd_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err",
+	{ .int_msk = BIT(5),
+	  .msg = "gro_context_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err",
+	{ .int_msk = BIT(6),
+	  .msg = "rx_stash_cfg_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err",
+	{ .int_msk = BIT(7),
+	  .msg = "axi_rd_fbd_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error tm_sch_int[] = {
-	{ .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "tm_sch_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err",
+	{ .int_msk = BIT(2),
+	  .msg = "tm_sch_port_shap_sub_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err",
+	{ .int_msk = BIT(3),
+	  .msg = "tm_sch_port_shap_sub_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
+	{ .int_msk = BIT(4),
+	  .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
+	{ .int_msk = BIT(5),
+	  .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
+	{ .int_msk = BIT(6),
+	  .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
+	{ .int_msk = BIT(7),
+	  .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
+	{ .int_msk = BIT(8),
+	  .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
+	{ .int_msk = BIT(9),
+	  .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
+	{ .int_msk = BIT(10),
+	  .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
+	{ .int_msk = BIT(11),
+	  .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err",
+	{ .int_msk = BIT(12),
+	  .msg = "tm_sch_port_shap_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err",
+	{ .int_msk = BIT(13),
+	  .msg = "tm_sch_port_shap_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
+	{ .int_msk = BIT(14),
+	  .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
+	{ .int_msk = BIT(15),
+	  .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
+	{ .int_msk = BIT(16),
+	  .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
+	{ .int_msk = BIT(17),
+	  .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
+	{ .int_msk = BIT(18),
+	  .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
+	{ .int_msk = BIT(19),
+	  .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
+	{ .int_msk = BIT(20),
+	  .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
+	{ .int_msk = BIT(21),
+	  .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err",
+	{ .int_msk = BIT(22),
+	  .msg = "tm_sch_rq_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err",
+	{ .int_msk = BIT(23),
+	  .msg = "tm_sch_rq_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err",
+	{ .int_msk = BIT(24),
+	  .msg = "tm_sch_nq_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err",
+	{ .int_msk = BIT(25),
+	  .msg = "tm_sch_nq_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err",
+	{ .int_msk = BIT(26),
+	  .msg = "tm_sch_roce_up_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err",
+	{ .int_msk = BIT(27),
+	  .msg = "tm_sch_roce_up_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err",
+	{ .int_msk = BIT(28),
+	  .msg = "tm_sch_rcb_byte_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err",
+	{ .int_msk = BIT(29),
+	  .msg = "tm_sch_rcb_byte_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err",
+	{ .int_msk = BIT(30),
+	  .msg = "tm_sch_ssu_byte_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err",
+	{ .int_msk = BIT(31),
+	  .msg = "tm_sch_ssu_byte_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error qcn_fifo_int[] = {
-	{ .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err",
+	{ .int_msk = BIT(0),
+	  .msg = "qcn_shap_gp0_sch_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err",
+	{ .int_msk = BIT(1),
+	  .msg = "qcn_shap_gp0_sch_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err",
+	{ .int_msk = BIT(2),
+	  .msg = "qcn_shap_gp1_sch_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err",
+	{ .int_msk = BIT(3),
+	  .msg = "qcn_shap_gp1_sch_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err",
+	{ .int_msk = BIT(4),
+	  .msg = "qcn_shap_gp2_sch_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err",
+	{ .int_msk = BIT(5),
+	  .msg = "qcn_shap_gp2_sch_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err",
+	{ .int_msk = BIT(6),
+	  .msg = "qcn_shap_gp3_sch_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err",
+	{ .int_msk = BIT(7),
+	  .msg = "qcn_shap_gp3_sch_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err",
+	{ .int_msk = BIT(8),
+	  .msg = "qcn_shap_gp0_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err",
+	{ .int_msk = BIT(9),
+	  .msg = "qcn_shap_gp0_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err",
+	{ .int_msk = BIT(10),
+	  .msg = "qcn_shap_gp1_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err",
+	{ .int_msk = BIT(11),
+	  .msg = "qcn_shap_gp1_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err",
+	{ .int_msk = BIT(12),
+	  .msg = "qcn_shap_gp2_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err",
+	{ .int_msk = BIT(13),
+	  .msg = "qcn_shap_gp2_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err",
+	{ .int_msk = BIT(14),
+	  .msg = "qcn_shap_gp3_offset_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err",
+	{ .int_msk = BIT(15),
+	  .msg = "qcn_shap_gp3_offset_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err",
+	{ .int_msk = BIT(16),
+	  .msg = "qcn_byte_info_fifo_rd_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err",
+	{ .int_msk = BIT(17),
+	  .msg = "qcn_byte_info_fifo_wr_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error qcn_ecc_int[] = {
-	{ .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "qcn_byte_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err",
+	{ .int_msk = BIT(3),
+	  .msg = "qcn_time_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err",
+	{ .int_msk = BIT(5),
+	  .msg = "qcn_fb_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err",
+	{ .int_msk = BIT(7),
+	  .msg = "qcn_link_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err",
+	{ .int_msk = BIT(9),
+	  .msg = "qcn_rate_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err",
+	{ .int_msk = BIT(11),
+	  .msg = "qcn_tmplt_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
+	{ .int_msk = BIT(13),
+	  .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
+	{ .int_msk = BIT(15),
+	  .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
+	{ .int_msk = BIT(17),
+	  .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
+	{ .int_msk = BIT(19),
+	  .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
+	{ .int_msk = BIT(21),
+	  .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ncsi_ecc_int[] = {
-	{ .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err",
+	{ .int_msk = BIT(1),
+	  .msg = "ncsi_tx_ecc_mbit_err",
 	  .reset_level = HNS3_NONE_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
-	{ .int_msk = BIT(0), .msg = "ig_mac_inf_int",
+	{ .int_msk = BIT(0),
+	  .msg = "ig_mac_inf_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(1), .msg = "ig_host_inf_int",
+	{ .int_msk = BIT(1),
+	  .msg = "ig_host_inf_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "ig_roc_buf_int",
+	{ .int_msk = BIT(2),
+	  .msg = "ig_roc_buf_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "ig_host_data_fifo_int",
+	{ .int_msk = BIT(3),
+	  .msg = "ig_host_data_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "ig_host_key_fifo_int",
+	{ .int_msk = BIT(4),
+	  .msg = "ig_host_key_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "tx_qcn_fifo_int",
+	{ .int_msk = BIT(5),
+	  .msg = "tx_qcn_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "rx_qcn_fifo_int",
+	{ .int_msk = BIT(6),
+	  .msg = "rx_qcn_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int",
+	{ .int_msk = BIT(7),
+	  .msg = "tx_pf_rd_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int",
+	{ .int_msk = BIT(8),
+	  .msg = "rx_pf_rd_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(9), .msg = "qm_eof_fifo_int",
+	{ .int_msk = BIT(9),
+	  .msg = "qm_eof_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(10), .msg = "mb_rlt_fifo_int",
+	{ .int_msk = BIT(10),
+	  .msg = "mb_rlt_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int",
+	{ .int_msk = BIT(11),
+	  .msg = "dup_uncopy_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int",
+	{ .int_msk = BIT(12),
+	  .msg = "dup_cnt_rd_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int",
+	{ .int_msk = BIT(13),
+	  .msg = "dup_cnt_drop_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int",
+	{ .int_msk = BIT(14),
+	  .msg = "dup_cnt_wrb_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(15), .msg = "host_cmd_fifo_int",
+	{ .int_msk = BIT(15),
+	  .msg = "host_cmd_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(16), .msg = "mac_cmd_fifo_int",
+	{ .int_msk = BIT(16),
+	  .msg = "mac_cmd_fifo_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int",
+	{ .int_msk = BIT(17),
+	  .msg = "host_cmd_bitmap_empty_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int",
+	{ .int_msk = BIT(18),
+	  .msg = "mac_cmd_bitmap_empty_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(19), .msg = "dup_bitmap_empty_int",
+	{ .int_msk = BIT(19),
+	  .msg = "dup_bitmap_empty_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int",
+	{ .int_msk = BIT(20),
+	  .msg = "out_queue_bitmap_empty_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int",
+	{ .int_msk = BIT(21),
+	  .msg = "bank2_bitmap_empty_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int",
+	{ .int_msk = BIT(22),
+	  .msg = "bank1_bitmap_empty_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int",
+	{ .int_msk = BIT(23),
+	  .msg = "bank0_bitmap_empty_int",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ssu_ets_tcg_int[] = {
-	{ .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg",
+	{ .int_msk = BIT(0),
+	  .msg = "ets_rd_int_rx_tcg",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg",
+	{ .int_msk = BIT(1),
+	  .msg = "ets_wr_int_rx_tcg",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg",
+	{ .int_msk = BIT(2),
+	  .msg = "ets_rd_int_tx_tcg",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg",
+	{ .int_msk = BIT(3),
+	  .msg = "ets_wr_int_tx_tcg",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error igu_egu_tnl_int[] = {
-	{ .int_msk = BIT(0), .msg = "rx_buf_overflow",
+	{ .int_msk = BIT(0),
+	  .msg = "rx_buf_overflow",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow",
+	{ .int_msk = BIT(1),
+	  .msg = "rx_stp_fifo_overflow",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow",
+	{ .int_msk = BIT(2),
+	  .msg = "rx_stp_fifo_underflow",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "tx_buf_overflow",
+	{ .int_msk = BIT(3),
+	  .msg = "tx_buf_overflow",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "tx_buf_underrun",
+	{ .int_msk = BIT(4),
+	  .msg = "tx_buf_underrun",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "rx_stp_buf_overflow",
+	{ .int_msk = BIT(5),
+	  .msg = "rx_stp_buf_overflow",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error ssu_port_based_err_int[] = {
-	{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
+	{ .int_msk = BIT(0),
+	  .msg = "roc_pkt_without_key_port",
 	  .reset_level = HNS3_FUNC_RESET },
-	{ .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port",
+	{ .int_msk = BIT(1),
+	  .msg = "tpu_pkt_without_key_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(2), .msg = "igu_pkt_without_key_port",
+	{ .int_msk = BIT(2),
+	  .msg = "igu_pkt_without_key_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(3), .msg = "roc_eof_mis_match_port",
+	{ .int_msk = BIT(3),
+	  .msg = "roc_eof_mis_match_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port",
+	{ .int_msk = BIT(4),
+	  .msg = "tpu_eof_mis_match_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(5), .msg = "igu_eof_mis_match_port",
+	{ .int_msk = BIT(5),
+	  .msg = "igu_eof_mis_match_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(6), .msg = "roc_sof_mis_match_port",
+	{ .int_msk = BIT(6),
+	  .msg = "roc_sof_mis_match_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port",
+	{ .int_msk = BIT(7),
+	  .msg = "tpu_sof_mis_match_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(8), .msg = "igu_sof_mis_match_port",
+	{ .int_msk = BIT(8),
+	  .msg = "igu_sof_mis_match_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(11), .msg = "ets_rd_int_rx_port",
+	{ .int_msk = BIT(11),
+	  .msg = "ets_rd_int_rx_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(12), .msg = "ets_wr_int_rx_port",
+	{ .int_msk = BIT(12),
+	  .msg = "ets_wr_int_rx_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(13), .msg = "ets_rd_int_tx_port",
+	{ .int_msk = BIT(13),
+	  .msg = "ets_rd_int_tx_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = BIT(14), .msg = "ets_wr_int_tx_port",
+	{ .int_msk = BIT(14),
+	  .msg = "ets_wr_int_tx_port",
 	  .reset_level = HNS3_GLOBAL_RESET },
-	{ .int_msk = 0, .msg = NULL,
+	{ .int_msk = 0,
+	  .msg = NULL,
 	  .reset_level = HNS3_NONE_RESET}
 };
 
 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
-	{ .desc_offset = 0, .data_offset = 0,
+	{ .desc_offset = 0,
+	  .data_offset = 0,
 	  .msg = "IMP_TCM_ECC_INT_STS",
 	  .hw_err = imp_tcm_ecc_int },
-	{ .desc_offset = 0, .data_offset = 1,
+	{ .desc_offset = 0,
+	  .data_offset = 1,
 	  .msg = "CMDQ_MEM_ECC_INT_STS",
 	  .hw_err = cmdq_mem_ecc_int },
-	{ .desc_offset = 0, .data_offset = 2,
+	{ .desc_offset = 0,
+	  .data_offset = 2,
 	  .msg = "IMP_RD_POISON_INT_STS",
 	  .hw_err = imp_rd_poison_int },
-	{ .desc_offset = 0, .data_offset = 3,
+	{ .desc_offset = 0,
+	  .data_offset = 3,
 	  .msg = "TQP_INT_ECC_INT_STS",
 	  .hw_err = tqp_int_ecc_int },
-	{ .desc_offset = 0, .data_offset = 4,
+	{ .desc_offset = 0,
+	  .data_offset = 4,
 	  .msg = "MSIX_ECC_INT_STS",
 	  .hw_err = msix_ecc_int },
-	{ .desc_offset = 2, .data_offset = 2,
+	{ .desc_offset = 2,
+	  .data_offset = 2,
 	  .msg = "SSU_ECC_MULTI_BIT_INT_0",
 	  .hw_err = ssu_ecc_multi_bit_int_0 },
-	{ .desc_offset = 2, .data_offset = 3,
+	{ .desc_offset = 2,
+	  .data_offset = 3,
 	  .msg = "SSU_ECC_MULTI_BIT_INT_1",
 	  .hw_err = ssu_ecc_multi_bit_int_1 },
-	{ .desc_offset = 2, .data_offset = 4,
+	{ .desc_offset = 2,
+	  .data_offset = 4,
 	  .msg = "SSU_COMMON_ERR_INT",
 	  .hw_err = ssu_common_ecc_int },
-	{ .desc_offset = 3, .data_offset = 0,
+	{ .desc_offset = 3,
+	  .data_offset = 0,
 	  .msg = "IGU_INT_STS",
 	  .hw_err = igu_int },
-	{ .desc_offset = 4, .data_offset = 1,
+	{ .desc_offset = 4,
+	  .data_offset = 1,
 	  .msg = "PPP_MPF_ABNORMAL_INT_ST1",
 	  .hw_err = ppp_mpf_abnormal_int_st1 },
-	{ .desc_offset = 4, .data_offset = 3,
+	{ .desc_offset = 4,
+	  .data_offset = 3,
 	  .msg = "PPP_MPF_ABNORMAL_INT_ST3",
 	  .hw_err = ppp_mpf_abnormal_int_st3 },
-	{ .desc_offset = 5, .data_offset = 1,
+	{ .desc_offset = 5,
+	  .data_offset = 1,
 	  .msg = "PPU_MPF_ABNORMAL_INT_ST1",
 	  .hw_err = ppu_mpf_abnormal_int_st1 },
-	{ .desc_offset = 5, .data_offset = 2,
+	{ .desc_offset = 5,
+	  .data_offset = 2,
 	  .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
 	  .hw_err = ppu_mpf_abnormal_int_st2_ras },
-	{ .desc_offset = 5, .data_offset = 3,
+	{ .desc_offset = 5,
+	  .data_offset = 3,
 	  .msg = "PPU_MPF_ABNORMAL_INT_ST3",
 	  .hw_err = ppu_mpf_abnormal_int_st3 },
-	{ .desc_offset = 6, .data_offset = 0,
+	{ .desc_offset = 6,
+	  .data_offset = 0,
 	  .msg = "TM_SCH_RINT",
 	  .hw_err = tm_sch_int },
-	{ .desc_offset = 7, .data_offset = 0,
+	{ .desc_offset = 7,
+	  .data_offset = 0,
 	  .msg = "QCN_FIFO_RINT",
 	  .hw_err = qcn_fifo_int },
-	{ .desc_offset = 7, .data_offset = 1,
+	{ .desc_offset = 7,
+	  .data_offset = 1,
 	  .msg = "QCN_ECC_RINT",
 	  .hw_err = qcn_ecc_int },
-	{ .desc_offset = 9, .data_offset = 0,
+	{ .desc_offset = 9,
+	  .data_offset = 0,
 	  .msg = "NCSI_ECC_INT_RPT",
 	  .hw_err = ncsi_ecc_int },
-	{ .desc_offset = 0, .data_offset = 0,
+	{ .desc_offset = 0,
+	  .data_offset = 0,
 	  .msg = NULL,
 	  .hw_err = NULL }
 };
 
 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
-	{ .desc_offset = 0, .data_offset = 0,
+	{ .desc_offset = 0,
+	  .data_offset = 0,
 	  .msg = "SSU_PORT_BASED_ERR_INT_RAS",
 	  .hw_err = ssu_port_based_err_int },
-	{ .desc_offset = 0, .data_offset = 1,
+	{ .desc_offset = 0,
+	  .data_offset = 1,
 	  .msg = "SSU_FIFO_OVERFLOW_INT",
 	  .hw_err = ssu_fifo_overflow_int },
-	{ .desc_offset = 0, .data_offset = 2,
+	{ .desc_offset = 0,
+	  .data_offset = 2,
 	  .msg = "SSU_ETS_TCG_INT",
 	  .hw_err = ssu_ets_tcg_int },
-	{ .desc_offset = 1, .data_offset = 0,
+	{ .desc_offset = 1,
+	  .data_offset = 0,
 	  .msg = "IGU_EGU_TNL_INT_STS",
 	  .hw_err = igu_egu_tnl_int },
-	{ .desc_offset = 3, .data_offset = 0,
+	{ .desc_offset = 3,
+	  .data_offset = 0,
 	  .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
 	  .hw_err = ppu_pf_abnormal_int_ras },
-	{ .desc_offset = 0, .data_offset = 0,
+	{ .desc_offset = 0,
+	  .data_offset = 0,
 	  .msg = NULL,
 	  .hw_err = NULL }
 };
 
 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
-	{ .desc_offset = 1, .data_offset = 0,
+	{ .desc_offset = 1,
+	  .data_offset = 0,
 	  .msg = "MAC_AFIFO_TNL_INT_R",
 	  .hw_err = mac_afifo_tnl_int },
-	{ .desc_offset = 5, .data_offset = 2,
+	{ .desc_offset = 5,
+	  .data_offset = 2,
 	  .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
 	  .hw_err = ppu_mpf_abnormal_int_st2_msix },
-	{ .desc_offset = 0, .data_offset = 0,
+	{ .desc_offset = 0,
+	  .data_offset = 0,
 	  .msg = NULL,
 	  .hw_err = NULL }
 };
 
 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
-	{ .desc_offset = 0, .data_offset = 0,
+	{ .desc_offset = 0,
+	  .data_offset = 0,
 	  .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
 	  .hw_err = ssu_port_based_pf_int },
-	{ .desc_offset = 2, .data_offset = 0,
+	{ .desc_offset = 2,
+	  .data_offset = 0,
 	  .msg = "PPP_PF_ABNORMAL_INT_ST0",
 	  .hw_err = ppp_pf_abnormal_int },
-	{ .desc_offset = 3, .data_offset = 0,
+	{ .desc_offset = 3,
+	  .data_offset = 0,
 	  .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
 	  .hw_err = ppu_pf_abnormal_int_msix },
-	{ .desc_offset = 0, .data_offset = 0,
+	{ .desc_offset = 0,
+	  .data_offset = 0,
 	  .msg = NULL,
 	  .hw_err = NULL }
 };
diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
index 85316ca..285c06d 100644
--- a/drivers/net/hns3/hns3_rxtx.c
+++ b/drivers/net/hns3/hns3_rxtx.c
@@ -1564,7 +1564,6 @@ hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
 
 	vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
 			RTE_PKTMBUF_HEADROOM);
-
 	if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
 		return -EINVAL;
 
diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c
index c590647..91168ac 100644
--- a/drivers/net/hns3/hns3_stats.c
+++ b/drivers/net/hns3/hns3_stats.c
@@ -679,7 +679,6 @@ hns3_get_queue_stats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 			(*count)++;
 		}
 	}
-
 }
 
 void
