From patchwork Thu Oct 15 06:38:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 80835 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E8B0A04DB; Thu, 15 Oct 2020 08:38:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 75F1D1DC9F; Thu, 15 Oct 2020 08:38:33 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 3C7ED1DC89 for ; Thu, 15 Oct 2020 08:38:30 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from matan@nvidia.com) with SMTP; 15 Oct 2020 09:38:23 +0300 Received: from nvidia.com (pegasus25.mtr.labs.mlnx [10.210.16.10]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09F6cNVt014993; Thu, 15 Oct 2020 09:38:23 +0300 From: Matan Azrad To: dev@dpdk.org Cc: Viacheslav Ovsiienko Date: Thu, 15 Oct 2020 06:38:11 +0000 Message-Id: <1602743893-345348-2-git-send-email-matan@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1602743893-345348-1-git-send-email-matan@nvidia.com> References: <1602743893-345348-1-git-send-email-matan@nvidia.com> Subject: [dpdk-dev] [PATCH 2/4] net/mlx5: fix Tx queue release X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The HW objects of the Tx queue is created/destroyed in the device start\stop stage while the ethdev configurations for the Tx queue starts from the tx_queue_setup stage. The PMD should save all the last configurations it got from the ethdev and to apply them to the device in the dev_start operation. Wrongly, last code added to mitigate the reference counters didn't take into account the above rule and combined the configurations and HW objects to be created\destroyed together. This causes to memory leak and other memory issues. Make sure the HW object is released in stop operation when there is no any reference to it while the configurations stay saved. Fixes: 17a57183c0eb ("net/mlx5: mitigate Tx queue reference counters") Signed-off-by: Matan Azrad Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_rxtx.h | 2 +- drivers/net/mlx5/mlx5_txq.c | 21 ++++++++++++--------- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index c3734e3..b243b6f 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -269,7 +269,7 @@ enum mlx5_txq_type { /* TX queue control descriptor. */ struct mlx5_txq_ctrl { LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ + uint32_t refcnt; /* Reference counter. */ unsigned int socket; /* CPU socket ID for allocations. */ enum mlx5_txq_type type; /* The txq ctrl type. */ unsigned int max_inline_data; /* Max inline data. */ diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index af84f5f..9c2dd2a 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -1121,7 +1121,7 @@ struct mlx5_txq_ctrl * rte_errno = ENOMEM; goto error; } - rte_atomic32_inc(&tmpl->refcnt); + __atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED); tmpl->type = MLX5_TXQ_TYPE_STANDARD; LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next); return tmpl; @@ -1165,7 +1165,7 @@ struct mlx5_txq_ctrl * tmpl->txq.idx = idx; tmpl->hairpin_conf = *hairpin_conf; tmpl->type = MLX5_TXQ_TYPE_HAIRPIN; - rte_atomic32_inc(&tmpl->refcnt); + __atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED); LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next); return tmpl; } @@ -1190,7 +1190,7 @@ struct mlx5_txq_ctrl * if (txq_data) { ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq); - rte_atomic32_inc(&ctrl->refcnt); + __atomic_add_fetch(&ctrl->refcnt, 1, __ATOMIC_RELAXED); } return ctrl; } @@ -1215,7 +1215,7 @@ struct mlx5_txq_ctrl * if (!(*priv->txqs)[idx]) return 0; txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); - if (!rte_atomic32_dec_and_test(&txq_ctrl->refcnt)) + if (__atomic_sub_fetch(&txq_ctrl->refcnt, 1, __ATOMIC_RELAXED) > 1) return 1; if (txq_ctrl->obj) { priv->obj_ops.txq_obj_release(txq_ctrl->obj); @@ -1229,12 +1229,15 @@ struct mlx5_txq_ctrl * txq_ctrl->txq.fcqs = NULL; } txq_free_elts(txq_ctrl); - mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh); } - LIST_REMOVE(txq_ctrl, next); - mlx5_free(txq_ctrl); - (*priv->txqs)[idx] = NULL; dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED; + if (!__atomic_load_n(&txq_ctrl->refcnt, __ATOMIC_RELAXED)) { + if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) + mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh); + LIST_REMOVE(txq_ctrl, next); + mlx5_free(txq_ctrl); + (*priv->txqs)[idx] = NULL; + } return 0; } @@ -1258,7 +1261,7 @@ struct mlx5_txq_ctrl * if (!(*priv->txqs)[idx]) return -1; txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); - return (rte_atomic32_read(&txq->refcnt) == 1); + return (__atomic_load_n(&txq->refcnt, __ATOMIC_RELAXED) == 1); } /**