[v2,2/3] common/mlx5: add counter batch query ID alignment define
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Commit Message
The counter batch query requires ID to be aligned with 4.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
---
drivers/common/mlx5/mlx5_prm.h | 3 +++
1 file changed, 3 insertions(+)
Comments
On 7/22/2020 8:58 AM, Suanming Mou wrote:
> The counter batch query requires ID to be aligned with 4.
>
> Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
> Acked-by: Matan Azrad <matan@mellanox.com>
> ---
> drivers/common/mlx5/mlx5_prm.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
> index cb5f968..8565d25 100644
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -818,6 +818,9 @@ enum {
> */
> #define MLX5_CNT_BATCH_OFFSET 0x800000
>
> +/* The counter batch query requires ID align with 4. */
> +#define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
> +
> /* Flow counters. */
> struct mlx5_ifc_alloc_flow_counter_out_bits {
> u8 status[0x8];
>
Having only macro separated from usage is not very helpful, squashing this
commit with 3/3 where the macro is used in 'next-net' repo.
@@ -818,6 +818,9 @@ enum {
*/
#define MLX5_CNT_BATCH_OFFSET 0x800000
+/* The counter batch query requires ID align with 4. */
+#define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
+
/* Flow counters. */
struct mlx5_ifc_alloc_flow_counter_out_bits {
u8 status[0x8];