[v6,3/4] qat: use WC store to update queue tail registers
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Commit Message
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
---
drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
Comments
On Mon, Jul 13, 2020 at 01:27:26PM +0100, Radu Nicolau wrote:
> Performance improvement: use a write combining store
> instead of a regular mmio write to update queue tail
> registers.
>
> Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
> ---
minor nit, I think the subject prefix on the patch should be crypto/qat.
> -----Original Message-----
> From: Bruce Richardson <bruce.richardson@intel.com>
> Sent: Monday, July 13, 2020 1:45 PM
> To: Nicolau, Radu <radu.nicolau@intel.com>
> Cc: dev@dpdk.org; Xing, Beilei <beilei.xing@intel.com>; Guo, Jia <jia.guo@intel.com>; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>; jerinjacobk@gmail.com; david.marchand@redhat.com; Trahe, Fiona
> <fiona.trahe@intel.com>; Zhao1, Wei <wei.zhao1@intel.com>
> Subject: Re: [PATCH v6 3/4] qat: use WC store to update queue tail registers
>
> On Mon, Jul 13, 2020 at 01:27:26PM +0100, Radu Nicolau wrote:
> > Performance improvement: use a write combining store
> > instead of a regular mmio write to update queue tail
> > registers.
> >
> > Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
> > ---
> minor nit, I think the subject prefix on the patch should be crypto/qat.
when it affects all qat PMDs, i.e. crypto sym, crypto asym and compression, as
this does we usually use drivers/qat
On Mon, Jul 13, 2020 at 01:52:24PM +0100, Trahe, Fiona wrote:
>
>
> > -----Original Message-----
> > From: Bruce Richardson <bruce.richardson@intel.com>
> > Sent: Monday, July 13, 2020 1:45 PM
> > To: Nicolau, Radu <radu.nicolau@intel.com>
> > Cc: dev@dpdk.org; Xing, Beilei <beilei.xing@intel.com>; Guo, Jia <jia.guo@intel.com>; Ananyev, Konstantin
> > <konstantin.ananyev@intel.com>; jerinjacobk@gmail.com; david.marchand@redhat.com; Trahe, Fiona
> > <fiona.trahe@intel.com>; Zhao1, Wei <wei.zhao1@intel.com>
> > Subject: Re: [PATCH v6 3/4] qat: use WC store to update queue tail registers
> >
> > On Mon, Jul 13, 2020 at 01:27:26PM +0100, Radu Nicolau wrote:
> > > Performance improvement: use a write combining store
> > > instead of a regular mmio write to update queue tail
> > > registers.
> > >
> > > Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
> > > ---
> > minor nit, I think the subject prefix on the patch should be crypto/qat.
> when it affects all qat PMDs, i.e. crypto sym, crypto asym and compression, as
> this does we usually use drivers/qat
Ah, yes, sorry, I forgot that there was more than one qat directory in
drivers. In this case, the changes are in common only, so common/qat would
seem to be the right prefix. Not that it matters to the patch
functionality, mind... :-)
@@ -9,6 +9,8 @@
/* CSR write macro */
#define ADF_CSR_WR(csrAddr, csrOffset, val) \
rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
+#define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \
+ rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset))
/* CSR read macro */
#define ADF_CSR_RD(csrAddr, csrOffset) \
@@ -110,10 +112,10 @@ do { \
ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
} while (0)
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
- ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+ ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_RING_CSR_RING_HEAD + (ring << 2), value)
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
- ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+ ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_RING_CSR_RING_TAIL + (ring << 2), value)
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
do { \