diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index 7fa4276e9e..34b1d06632 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -198,6 +198,7 @@ M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,			\
 			       cpt_inline_ipsec_cfg_msg, msg_rsp)	\
 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg,			\
 			       cpt_rx_inline_lf_cfg_msg, msg_rsp)	\
+M(CPT_GET_CAPS,		0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)	\
 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
 M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry,			\
 				npc_mcam_alloc_entry_req,		\
@@ -1258,6 +1259,38 @@ struct cpt_rx_inline_lf_cfg_msg {
 	uint16_t __otx2_io sso_pf_func;
 };
 
+enum cpt_eng_type {
+	CPT_ENG_TYPE_AE = 1,
+	CPT_ENG_TYPE_SE = 2,
+	CPT_ENG_TYPE_IE = 3,
+	CPT_MAX_ENG_TYPES,
+};
+
+/* CPT HW capabilities */
+union cpt_eng_caps {
+	uint64_t __otx2_io u;
+	struct {
+		uint64_t __otx2_io reserved_0_4:5;
+		uint64_t __otx2_io mul:1;
+		uint64_t __otx2_io sha1_sha2:1;
+		uint64_t __otx2_io chacha20:1;
+		uint64_t __otx2_io zuc_snow3g:1;
+		uint64_t __otx2_io sha3:1;
+		uint64_t __otx2_io aes:1;
+		uint64_t __otx2_io kasumi:1;
+		uint64_t __otx2_io des:1;
+		uint64_t __otx2_io crc:1;
+		uint64_t __otx2_io reserved_14_63:50;
+	};
+};
+
+struct cpt_caps_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint16_t __otx2_io cpt_pf_drv_version;
+	uint8_t __otx2_io cpt_revision;
+	union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
+};
+
 /* NPC mbox message structs */
 
 #define NPC_MCAM_ENTRY_INVALID	0xFFFF
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index 6ffbc2eb7c..77aa315dc0 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -14,6 +14,7 @@
 
 #include "otx2_common.h"
 #include "otx2_cryptodev.h"
+#include "otx2_cryptodev_capabilities.h"
 #include "otx2_cryptodev_mbox.h"
 #include "otx2_cryptodev_ops.h"
 #include "otx2_dev.h"
@@ -96,6 +97,12 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 
 	CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
 
+	ret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps);
+	if (ret) {
+		CPT_LOG_ERR("Could not determine hardware capabilities");
+		goto otx2_dev_fini;
+	}
+
 	dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
 			     RTE_CRYPTODEV_FF_HW_ACCELERATED |
 			     RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
index c0aa661b3b..e7a1730b22 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -29,6 +29,8 @@ struct otx2_cpt_vf {
 	/**< MSI-X offsets */
 	uint8_t err_intr_registered:1;
 	/**< Are error interrupts registered? */
+	union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
+	/**< CPT device capabilities */
 };
 
 #define CPT_LOGTYPE otx2_cpt_logtype
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
index 3eb3d8532c..9e18c4eee0 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -5,115 +5,87 @@
 #include <rte_cryptodev.h>
 
 #include "otx2_cryptodev_capabilities.h"
+#include "otx2_mbox.h"
 
-static const struct
-rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
-	/* Symmetric capabilities */
-	{	/* NULL (AUTH) */
-		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
-		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
-			{.auth = {
-				.algo = RTE_CRYPTO_AUTH_NULL,
-				.block_size = 1,
-				.key_size = {
-					.min = 0,
-					.max = 0,
-					.increment = 0
-				},
-				.digest_size = {
-					.min = 0,
-					.max = 0,
-					.increment = 0
-				},
-			}, },
-		}, },
-	},
-	{	/* AES GMAC (AUTH) */
-		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
-		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
-			{.auth = {
-				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
-				.block_size = 16,
-				.key_size = {
-					.min = 16,
-					.max = 32,
-					.increment = 8
-				},
-				.digest_size = {
-					.min = 8,
-					.max = 16,
-					.increment = 4
-				},
-				.iv_size = {
-					.min = 12,
-					.max = 12,
-					.increment = 0
-				}
-			}, }
+#define CPT_EGRP_GET(hw_caps, name, egrp) do {	\
+	if ((hw_caps[CPT_ENG_TYPE_SE].name) &&	\
+	    (hw_caps[CPT_ENG_TYPE_IE].name))	\
+		*egrp = OTX2_CPT_EGRP_SE_IE;	\
+	else if (hw_caps[CPT_ENG_TYPE_SE].name)	\
+		*egrp = OTX2_CPT_EGRP_SE;	\
+	else if (hw_caps[CPT_ENG_TYPE_AE].name)	\
+		*egrp = OTX2_CPT_EGRP_AE;	\
+	else					\
+		*egrp = OTX2_CPT_EGRP_MAX;	\
+} while (0)
+
+#define CPT_CAPS_ADD(hw_caps, name) do {				\
+	enum otx2_cpt_egrp egrp;					\
+	CPT_EGRP_GET(hw_caps, name, &egrp);				\
+	if (egrp < OTX2_CPT_EGRP_MAX)					\
+		cpt_caps_add(caps_##name, RTE_DIM(caps_##name));	\
+} while (0)
+
+#define OTX2_CPT_MAX_CAPS 34
+
+static struct rte_cryptodev_capabilities otx2_cpt_caps[OTX2_CPT_MAX_CAPS];
+
+static const struct rte_cryptodev_capabilities caps_mul[] = {
+	{	/* RSA */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
+				.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+					(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+					(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+					(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+				{.modlen = {
+					.min = 17,
+					.max = 1024,
+					.increment = 1
+				}, }
+			}
 		}, }
 	},
-	{	/* KASUMI (F9) */
-		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
-		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
-			{.auth = {
-				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,
-				.block_size = 8,
-				.key_size = {
-					.min = 16,
-					.max = 16,
-					.increment = 0
-				},
-				.digest_size = {
-					.min = 4,
-					.max = 4,
-					.increment = 0
-				},
-			}, }
+	{	/* MOD_EXP */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
+				.op_types = 0,
+				{.modlen = {
+					.min = 17,
+					.max = 1024,
+					.increment = 1
+				}, }
+			}
 		}, }
 	},
-	{	/* MD5 */
-		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
-		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
-			{.auth = {
-				.algo = RTE_CRYPTO_AUTH_MD5,
-				.block_size = 64,
-				.key_size = {
-					.min = 0,
-					.max = 0,
-					.increment = 0
-				},
-				.digest_size = {
-					.min = 16,
-					.max = 16,
-					.increment = 0
-				},
-			}, }
-		}, }
+	{	/* ECDSA */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,
+				.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+					(1 << RTE_CRYPTO_ASYM_OP_VERIFY)),
+				}
+			},
+		}
 	},
-	{	/* MD5 HMAC */
-		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
-		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
-			{.auth = {
-				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
-				.block_size = 64,
-				.key_size = {
-					.min = 8,
-					.max = 64,
-					.increment = 8
-				},
-				.digest_size = {
-					.min = 16,
-					.max = 16,
-					.increment = 0
-				},
-			}, }
-		}, }
+	{	/* ECPM */
+		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+		{.asym = {
+			.xform_capa = {
+				.xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,
+				.op_types = 0
+				}
+			},
+		}
 	},
+};
+
+static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {
 	{	/* SHA1 */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
@@ -147,9 +119,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 					.increment = 1
 				},
 				.digest_size = {
-					.min = 20,
+					.min = 12,
 					.max = 20,
-					.increment = 0
+					.increment = 8
 				},
 			}, }
 		}, }
@@ -227,9 +199,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 					.increment = 1
 				},
 				.digest_size = {
-					.min = 32,
+					.min = 16,
 					.max = 32,
-					.increment = 0
+					.increment = 16
 				},
 			}, }
 		}, }
@@ -267,9 +239,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 					.increment = 1
 				},
 				.digest_size = {
-					.min = 48,
+					.min = 24,
 					.max = 48,
-					.increment = 0
+					.increment = 24
 					},
 			}, }
 		}, }
@@ -307,28 +279,66 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 					.increment = 1
 				},
 				.digest_size = {
-					.min = 64,
+					.min = 32,
 					.max = 64,
-					.increment = 0
+					.increment = 32
 				},
 			}, }
 		}, }
 	},
-	{	/* SNOW 3G (UIA2) */
+	{	/* MD5 */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
 			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 			{.auth = {
-				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
-				.block_size = 16,
+				.algo = RTE_CRYPTO_AUTH_MD5,
+				.block_size = 64,
 				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
 					.min = 16,
 					.max = 16,
 					.increment = 0
 				},
+			}, }
+		}, }
+	},
+	{	/* MD5 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 8,
+					.max = 64,
+					.increment = 8
+				},
 				.digest_size = {
-					.min = 4,
-					.max = 4,
+					.min = 12,
+					.max = 16,
+					.increment = 4
+				},
+			}, }
+		}, }
+	},
+};
+
+static const struct rte_cryptodev_capabilities caps_zuc_snow3g[] = {
+	{	/* SNOW 3G (UEA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
 					.increment = 0
 				},
 				.iv_size = {
@@ -339,23 +349,18 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 			}, }
 		}, }
 	},
-	{	/* ZUC (EIA3) */
+	{	/* ZUC (EEA3) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
-			{.auth = {
-				.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
 				.block_size = 16,
 				.key_size = {
 					.min = 16,
 					.max = 16,
 					.increment = 0
 				},
-				.digest_size = {
-					.min = 4,
-					.max = 4,
-					.increment = 0
-				},
 				.iv_size = {
 					.min = 16,
 					.max = 16,
@@ -364,61 +369,79 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 			}, }
 		}, }
 	},
-	{	/* NULL (CIPHER) */
+	{	/* SNOW 3G (UIA2) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
-			{.cipher = {
-				.algo = RTE_CRYPTO_CIPHER_NULL,
-				.block_size = 1,
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+				.block_size = 16,
 				.key_size = {
-					.min = 0,
-					.max = 0,
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
 					.increment = 0
 				},
 				.iv_size = {
-					.min = 0,
-					.max = 0,
+					.min = 16,
+					.max = 16,
 					.increment = 0
 				}
-			}, },
+			}, }
 		}, }
 	},
-	{	/* 3DES CBC */
+	{	/* ZUC (EIA3) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
-			{.cipher = {
-				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
-				.block_size = 8,
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+				.block_size = 16,
 				.key_size = {
-					.min = 24,
-					.max = 24,
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
 					.increment = 0
 				},
 				.iv_size = {
-					.min = 8,
+					.min = 16,
 					.max = 16,
-					.increment = 8
+					.increment = 0
 				}
 			}, }
 		}, }
 	},
-	{	/* 3DES ECB */
+};
+
+static const struct rte_cryptodev_capabilities caps_aes[] = {
+	{	/* AES GMAC (AUTH) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
-			{.cipher = {
-				.algo = RTE_CRYPTO_CIPHER_3DES_ECB,
-				.block_size = 8,
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
+				.block_size = 16,
 				.key_size = {
-					.min = 24,
-					.max = 24,
-					.increment = 0
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
 				},
 				.iv_size = {
-					.min = 0,
-					.max = 0,
+					.min = 12,
+					.max = 12,
 					.increment = 0
 				}
 			}, }
@@ -484,26 +507,39 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 			}, }
 		}, }
 	},
-	{	/* DES CBC */
+	{	/* AES GCM */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
-			{.cipher = {
-				.algo = RTE_CRYPTO_CIPHER_DES_CBC,
-				.block_size = 8,
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+			{.aead = {
+				.algo = RTE_CRYPTO_AEAD_AES_GCM,
+				.block_size = 16,
 				.key_size = {
-					.min = 8,
-					.max = 8,
-					.increment = 0
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 16,
+					.increment = 1
+				},
+				.aad_size = {
+					.min = 0,
+					.max = 1024,
+					.increment = 1
 				},
 				.iv_size = {
-					.min = 8,
-					.max = 8,
+					.min = 12,
+					.max = 12,
 					.increment = 0
 				}
 			}, }
 		}, }
 	},
+};
+
+static const struct rte_cryptodev_capabilities caps_kasumi[] = {
 	{	/* KASUMI (F8) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
@@ -524,137 +560,163 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 			}, }
 		}, }
 	},
-	{	/* SNOW 3G (UEA2) */
+	{	/* KASUMI (F9) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
-			{.cipher = {
-				.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
-				.block_size = 16,
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+				.block_size = 8,
 				.key_size = {
 					.min = 16,
 					.max = 16,
 					.increment = 0
 				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+			}, }
+		}, }
+	},
+};
+
+static const struct rte_cryptodev_capabilities caps_des[] = {
+	{	/* 3DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
 				.iv_size = {
-					.min = 16,
+					.min = 8,
 					.max = 16,
+					.increment = 8
+				}
+			}, }
+		}, }
+	},
+	{	/* 3DES ECB */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_ECB,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
 					.increment = 0
 				}
 			}, }
 		}, }
 	},
-	{	/* ZUC (EEA3) */
+	{	/* DES CBC */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
 			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
 			{.cipher = {
-				.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
-				.block_size = 16,
+				.algo = RTE_CRYPTO_CIPHER_DES_CBC,
+				.block_size = 8,
 				.key_size = {
-					.min = 16,
-					.max = 16,
+					.min = 8,
+					.max = 8,
 					.increment = 0
 				},
 				.iv_size = {
-					.min = 16,
-					.max = 16,
+					.min = 8,
+					.max = 8,
 					.increment = 0
 				}
 			}, }
 		}, }
 	},
-	{	/* AES GCM */
+};
+
+static const struct rte_cryptodev_capabilities caps_null[] = {
+	{	/* NULL (AUTH) */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
-			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
-			{.aead = {
-				.algo = RTE_CRYPTO_AEAD_AES_GCM,
-				.block_size = 16,
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_NULL,
+				.block_size = 1,
 				.key_size = {
-					.min = 16,
-					.max = 32,
-					.increment = 8
+					.min = 0,
+					.max = 0,
+					.increment = 0
 				},
 				.digest_size = {
-					.min = 4,
-					.max = 16,
-					.increment = 1
+					.min = 0,
+					.max = 0,
+					.increment = 0
 				},
-				.aad_size = {
+			}, },
+		}, },
+	},
+	{	/* NULL (CIPHER) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_NULL,
+				.block_size = 1,
+				.key_size = {
 					.min = 0,
-					.max = 1024,
-					.increment = 1
+					.max = 0,
+					.increment = 0
 				},
 				.iv_size = {
-					.min = 12,
-					.max = 12,
+					.min = 0,
+					.max = 0,
 					.increment = 0
 				}
-			}, }
+			}, },
 		}, }
 	},
-	/* End of symmetric capabilities */
+};
 
-	/* Asymmetric capabilities */
-	{	/* RSA */
-		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
-		{.asym = {
-			.xform_capa = {
-				.xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
-				.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
-					(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
-					(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
-					(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
-				{.modlen = {
-					.min = 17,
-					.max = 1024,
-					.increment = 1
-				}, }
-			}
-		}, }
-	},
-	{	/* MOD_EXP */
-		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
-		{.asym = {
-			.xform_capa = {
-				.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
-				.op_types = 0,
-				{.modlen = {
-					.min = 17,
-					.max = 1024,
-					.increment = 1
-				}, }
-			}
-		}, }
-	},
-	{	/* ECDSA */
-		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
-		{.asym = {
-			.xform_capa = {
-				.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,
-				.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
-					(1 << RTE_CRYPTO_ASYM_OP_VERIFY)),
-				}
-			},
-		}
-	},
-	{	/* ECPM */
-		.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
-		{.asym = {
-			.xform_capa = {
-				.xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,
-				.op_types = 0
-				}
-			},
-		}
-	},
-	/* End of asymmetric capabilities */
+static const struct rte_cryptodev_capabilities caps_end[] = {
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
+static void
+cpt_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps)
+{
+	static int cur_pos;
+
+	if (cur_pos + nb_caps > OTX2_CPT_MAX_CAPS)
+		return;
+
+	memcpy(&otx2_cpt_caps[cur_pos], caps, nb_caps * sizeof(caps[0]));
+	cur_pos += nb_caps;
+}
+
 const struct rte_cryptodev_capabilities *
-otx2_cpt_capabilities_get(void)
+otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps)
 {
-	return otx2_cpt_capabilities;
+
+	CPT_CAPS_ADD(hw_caps, mul);
+	CPT_CAPS_ADD(hw_caps, sha1_sha2);
+	CPT_CAPS_ADD(hw_caps, zuc_snow3g);
+	CPT_CAPS_ADD(hw_caps, aes);
+	CPT_CAPS_ADD(hw_caps, kasumi);
+	CPT_CAPS_ADD(hw_caps, des);
+
+	cpt_caps_add(caps_null, RTE_DIM(caps_null));
+	cpt_caps_add(caps_end, RTE_DIM(caps_end));
+
+	return otx2_cpt_caps;
 }
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
index f103c32eda..e07a2a8c92 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
@@ -7,10 +7,20 @@
 
 #include <rte_cryptodev.h>
 
+#include "otx2_mbox.h"
+
+enum otx2_cpt_egrp {
+	OTX2_CPT_EGRP_SE = 0,
+	OTX2_CPT_EGRP_SE_IE = 1,
+	OTX2_CPT_EGRP_AE = 2,
+	OTX2_CPT_EGRP_MAX,
+};
+
 /*
  * Get capabilities list for the device
  *
  */
-const struct rte_cryptodev_capabilities *otx2_cpt_capabilities_get(void);
+const struct rte_cryptodev_capabilities *
+otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps);
 
 #endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index 6bb8316ec9..6028439de3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -14,6 +14,27 @@
 
 #include "cpt_pmd_logs.h"
 
+int
+otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,
+			      union cpt_eng_caps *hw_caps)
+{
+	struct otx2_cpt_vf *vf = dev->data->dev_private;
+	struct otx2_dev *otx2_dev = &vf->otx2_dev;
+	struct cpt_caps_rsp_msg *rsp;
+	int ret;
+
+	otx2_mbox_alloc_msg_cpt_caps_get(otx2_dev->mbox);
+
+	ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	memcpy(hw_caps, rsp->eng_caps,
+		sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);
+
+	return 0;
+}
+
 int
 otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
 			      uint16_t *nb_queues)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
index ae66b08461..4bc057774f 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -9,6 +9,9 @@
 
 #include "otx2_cryptodev_hw_access.h"
 
+int otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,
+			      union cpt_eng_caps *hw_caps);
+
 int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
 				  uint16_t *nb_queues);
 
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index ad292a08f7..132f599efd 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -1067,7 +1067,7 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
 	if (info != NULL) {
 		info->max_nb_queue_pairs = vf->max_queues;
 		info->feature_flags = dev->feature_flags;
-		info->capabilities = otx2_cpt_capabilities_get();
+		info->capabilities = otx2_cpt_capabilities_get(vf->hw_caps);
 		info->sym.max_nb_sessions = 0;
 		info->driver_id = otx2_cryptodev_driver_id;
 		info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index f83e36b486..1970187f88 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -10,12 +10,6 @@
 #define OTX2_CPT_MIN_HEADROOM_REQ	24
 #define OTX2_CPT_MIN_TAILROOM_REQ	8
 
-enum otx2_cpt_egrp {
-	OTX2_CPT_EGRP_SE = 0,
-	OTX2_CPT_EGRP_SE_IE = 1,
-	OTX2_CPT_EGRP_AE = 2
-};
-
 extern struct rte_cryptodev_ops otx2_cpt_ops;
 
 #endif /* _OTX2_CRYPTODEV_OPS_H_ */
