From patchwork Mon Apr 6 06:43:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 67854 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C92BA0577; Mon, 6 Apr 2020 08:43:15 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5556B1BEDC; Mon, 6 Apr 2020 08:43:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id D6CDC1BED8 for ; Mon, 6 Apr 2020 08:43:13 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0366ecXc012551; Sun, 5 Apr 2020 23:43:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=mBfKDFBlwexBhjGGA+uDZIDfrkJ3MUgYxj1P98wNj24=; b=mFR4KX9sq3bIWCWAyJNsANRdN+IKR8DeXELvpsyXXlpFTfqgazv3Lm50lLCari/x/M3J dcg6ER2kcynprjXS/03lKGjOFPp8DqvaOXfn4mpHsn7yGdbm2qVTHoVefDOdnxX63NBw FlBFlBCIYaPoBglXF2wmb/EflgoPS1jrxij50/4Z0Ciurx7IxUvjLDC/iHbDZ8K6hajZ SZwAWHeV6Kv9GYrOueYUbleJ05v/febAEKD0W87tHEj7+kcVv76/3EpN2DbVh6OnfJJB 4hyVzZSOT4FOOSMxqYwUUKUqFafRiG2QzNaozxYj/fPwCWEIe070r4DlH9MnyHKPMcSj rg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 306qkqw224-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 05 Apr 2020 23:43:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 5 Apr 2020 23:43:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 5 Apr 2020 23:43:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 5 Apr 2020 23:43:10 -0700 Received: from dc7-eodlnx03.marvell.com (dc7-eodlnx03.marvell.com [10.28.113.53]) by maili.marvell.com (Postfix) with ESMTP id 4B7F13F703F; Sun, 5 Apr 2020 23:43:08 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , "John McNamara" , Marko Kovacevic , Vamsi Attunuru CC: , Satheesh Paul A Date: Mon, 6 Apr 2020 12:13:03 +0530 Message-ID: <1586155384-1543-1-git-send-email-psatheesh@marvell.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-06_02:2020-04-03, 2020-04-06 signatures=0 Subject: [dpdk-dev] [PATCH v2] net/octeontx2: support for custom L2 header X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul A This patch adds SDP packet parsing support with custom L2 header, adds support to include a field from custom header for flow tag generation. Signed-off-by: Satheesh Paul A Acked-by: Jerin Jacob --- v2: No change. Resending after subscribing to dev@dpdk.org mailing list doc/guides/nics/octeontx2.rst | 2 +- drivers/common/octeontx2/hw/otx2_npc.h | 2 ++ drivers/common/octeontx2/otx2_mbox.h | 4 +++- drivers/net/octeontx2/otx2_ethdev.c | 6 ++++++ drivers/net/octeontx2/otx2_ethdev_devargs.c | 4 +++- drivers/net/octeontx2/otx2_rss.c | 5 +++++ 6 files changed, 20 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst index 60187ec..b615585 100644 --- a/doc/guides/nics/octeontx2.rst +++ b/doc/guides/nics/octeontx2.rst @@ -177,7 +177,7 @@ Runtime Config Options With the above configuration, higig2 will be enabled on that port and the traffic on this port should be higig2 traffic only. Supported switch header - types are "higig2" and "dsa". + types are "higig2", "dsa" and "chlen90b". - ``RSS tag as XOR`` (default ``0``) diff --git a/drivers/common/octeontx2/hw/otx2_npc.h b/drivers/common/octeontx2/hw/otx2_npc.h index 3dfc137..8083c78 100644 --- a/drivers/common/octeontx2/hw/otx2_npc.h +++ b/drivers/common/octeontx2/hw/otx2_npc.h @@ -31,6 +31,7 @@ (0x80008ull | (uint64_t)(a) << 6) #define NPC_AF_PKINDX_CPI_DEFX(a, b) \ (0x80020ull | (uint64_t)(a) << 6 | (uint64_t)(b) << 3) +#define NPC_AF_CHLEN90B_PKIND (0x3bull) #define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \ (0x100000ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6 | \ (uint64_t)(c) << 3) @@ -184,6 +185,7 @@ enum npc_kpu_la_ltype { NPC_LT_LA_IH_2_ETHER, NPC_LT_LA_HIGIG2_ETHER, NPC_LT_LA_IH_NIX_HIGIG2_ETHER, + NPC_LT_LA_CH_LEN_90B_ETHER, /* Custom L2 header of length 90 bytes */ }; enum npc_kpu_lb_ltype { diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h index d192d89..59a2f5e 100644 --- a/drivers/common/octeontx2/otx2_mbox.h +++ b/drivers/common/octeontx2/otx2_mbox.h @@ -90,7 +90,7 @@ struct mbox_msghdr { #define OTX2_MBOX_RSP_SIG (0xbeef) /* Signature, for validating corrupted msgs */ uint16_t __otx2_io sig; -#define OTX2_MBOX_VERSION (0x0004) +#define OTX2_MBOX_VERSION (0x0006) /* Version of msg's structure for this ID */ uint16_t __otx2_io ver; /* Offset of next msg within mailbox region */ @@ -341,6 +341,7 @@ struct npc_set_pkind { #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1) #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2) +#define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3) #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) uint64_t __otx2_io mode; #define PKIND_TX BIT_ULL(0) @@ -923,6 +924,7 @@ struct nix_rss_flowkey_cfg { #define FLOW_KEY_TYPE_INNR_UDP BIT(15) #define FLOW_KEY_TYPE_INNR_SCTP BIT(16) #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) +#define FLOW_KEY_TYPE_CH_LEN_90B BIT(18) #define FLOW_KEY_TYPE_L4_DST BIT(28) #define FLOW_KEY_TYPE_L4_SRC BIT(29) #define FLOW_KEY_TYPE_L3_DST BIT(30) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index e60f490..2f2f1b6 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -106,6 +106,12 @@ if (dev->npc_flow.switch_header_type == 0) return 0; + if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B && + !otx2_dev_is_sdp(dev)) { + otx2_err("chlen90b is not supported on non-SDP device"); + return -EINVAL; + } + /* Notify AF about higig2 config */ req = otx2_mbox_alloc_msg_npc_set_pkind(mbox); req->mode = dev->npc_flow.switch_header_type; diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c index f29f015..83868bc 100644 --- a/drivers/net/octeontx2/otx2_ethdev_devargs.c +++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c @@ -113,6 +113,8 @@ if (strcmp(value, "dsa") == 0) *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA; + if (strcmp(value, "chlen90b") == 0) + *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_LEN_90B; return 0; } @@ -185,5 +187,5 @@ OTX2_MAX_SQB_COUNT "=<8-512>" OTX2_FLOW_PREALLOC_SIZE "=<1-32>" OTX2_FLOW_MAX_PRIORITY "=<1-32>" - OTX2_SWITCH_HEADER_TYPE "=" + OTX2_SWITCH_HEADER_TYPE "=" OTX2_RSS_TAG_AS_XOR "=1"); diff --git a/drivers/net/octeontx2/otx2_rss.c b/drivers/net/octeontx2/otx2_rss.c index 7a8c8f3..a29441e 100644 --- a/drivers/net/octeontx2/otx2_rss.c +++ b/drivers/net/octeontx2/otx2_rss.c @@ -210,6 +210,11 @@ dev->rss_info.nix_rss = ethdev_rss; + if (ethdev_rss & ETH_RSS_L2_PAYLOAD && + dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B) { + flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B; + } + if (ethdev_rss & ETH_RSS_L3_SRC_ONLY) flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;