diff mbox series

[09/12] raw/ifpga_rawdev/base: update SEU register definition

Message ID 1564556752-19257-10-git-send-email-rosen.xu@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series Add PCIe AER disable and IRQ support for ipn3ke |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues

Commit Message

Xu, Rosen July 31, 2019, 7:05 a.m. UTC 
  From: Tianfei zhang <tianfei.zhang@intel.com>

Update the SEU registser definition.

Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
---
 drivers/raw/ifpga_rawdev/base/ifpga_defines.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
index b450cb1..8993cc6 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
@@ -1122,7 +1122,9 @@  struct feature_fme_ras_catfaterror {
 			u8  therm_catast_err:1;
 			/* Injected Catastrophic Error */
 			u8  injected_catast_err:1;
-			u64 rsvd:52;
+			/* SEU error on BMC */
+			u8  bmc_seu_catast_err:1;
+			u64 rsvd:51;
 		};
 	};
 };