[14/14] net/mlx5: add source vport match to the ingress rules
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Commit Message
For E-Switch configurations over multiport Infiniband devices
we should add source vport match to correctly distribute
traffic between representors.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
drivers/net/mlx5/mlx5_flow_dv.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
Comments
Thursday, March 21, 2019 10:11 AM, Viacheslav Ovsiienko:
> Subject: [PATCH 14/14] net/mlx5: add source vport match to the ingress rules
>
> For E-Switch configurations over multiport Infiniband devices we should add
> source vport match to correctly distribute traffic between representors.
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> ---
> drivers/net/mlx5/mlx5_flow_dv.c | 38
> ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c index b8943da..489b3bd 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -3095,6 +3095,29 @@ struct field_modify_info modify_tcp[] = { }
>
> /**
> + * Add source vport match to the specified matcher.
> + *
> + * @param[in, out] matcher
> + * Flow matcher.
> + * @param[in, out] key
> + * Flow matcher value.
> + * @param[in] port
> + * Source vport value to match
> + * @param[in] mask
> + * Mask
> + */
> +static void
> +flow_dv_translate_source_vport(void *matcher, void *key,
> + int16_t port, uint16_t mask)
> +{
> + void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher,
> misc_parameters);
> + void *misc_v = MLX5_ADDR_OF(fte_match_param, key,
> misc_parameters);
> +
> + MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
> + MLX5_SET(fte_match_set_misc, misc_v, source_port, port); }
> +
> +/**
> * Fill the flow with DV spec.
> *
> * @param[in] dev
> @@ -3389,6 +3412,21 @@ struct field_modify_info modify_tcp[] = {
> }
> dev_flow->dv.actions_n = actions_n;
> flow->actions = action_flags;
> + if (attr->ingress && !attr->transfer &&
> + (priv->representor || priv->master)) {
> + /* It was validated - we support unidirections flows only. */
> + assert(!attr->egress);
> + /*
> + * Add matching on source vport index only
> + * for ingress rules in E-Switch configurations.
> + */
> + flow_dv_translate_source_vport(matcher.mask.buf,
> + dev_flow->dv.value.buf,
> + priv->representor_id < 0 ?
> + priv->representor_id :
> + priv->representor_id + 1,
The vport of representor_id 0 will be 1?
Who owns vport 0?
> + 0xffff);
> + }
> for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
> int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
> void *match_mask = matcher.mask.buf;
> --
> 1.8.3.1
> -----Original Message-----
> From: Shahaf Shuler
> Sent: Thursday, March 21, 2019 14:15
> To: Slava Ovsiienko <viacheslavo@mellanox.com>; dev@dpdk.org
> Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the ingress
> rules
>
> Thursday, March 21, 2019 10:11 AM, Viacheslav Ovsiienko:
> > Subject: [PATCH 14/14] net/mlx5: add source vport match to the ingress
> > rules
> >
> > For E-Switch configurations over multiport Infiniband devices we
> > should add source vport match to correctly distribute traffic between
> representors.
> >
> > Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> > ---
> > drivers/net/mlx5/mlx5_flow_dv.c | 38
> > ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> > b/drivers/net/mlx5/mlx5_flow_dv.c index b8943da..489b3bd 100644
> > --- a/drivers/net/mlx5/mlx5_flow_dv.c
> > +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> > @@ -3095,6 +3095,29 @@ struct field_modify_info modify_tcp[] = { }
> >
> > /**
> > + * Add source vport match to the specified matcher.
> > + *
> > + * @param[in, out] matcher
> > + * Flow matcher.
> > + * @param[in, out] key
> > + * Flow matcher value.
> > + * @param[in] port
> > + * Source vport value to match
> > + * @param[in] mask
> > + * Mask
> > + */
> > +static void
> > +flow_dv_translate_source_vport(void *matcher, void *key,
> > + int16_t port, uint16_t mask) {
> > + void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher,
> > misc_parameters);
> > + void *misc_v = MLX5_ADDR_OF(fte_match_param, key,
> > misc_parameters);
> > +
> > + MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
> > + MLX5_SET(fte_match_set_misc, misc_v, source_port, port); }
> > +
> > +/**
> > * Fill the flow with DV spec.
> > *
> > * @param[in] dev
> > @@ -3389,6 +3412,21 @@ struct field_modify_info modify_tcp[] = {
> > }
> > dev_flow->dv.actions_n = actions_n;
> > flow->actions = action_flags;
> > + if (attr->ingress && !attr->transfer &&
> > + (priv->representor || priv->master)) {
> > + /* It was validated - we support unidirections flows only. */
> > + assert(!attr->egress);
> > + /*
> > + * Add matching on source vport index only
> > + * for ingress rules in E-Switch configurations.
> > + */
> > + flow_dv_translate_source_vport(matcher.mask.buf,
> > + dev_flow->dv.value.buf,
> > + priv->representor_id < 0 ?
> > + priv->representor_id :
> > + priv->representor_id + 1,
>
> The vport of representor_id 0 will be 1?
> Who owns vport 0?
PF.
There is the foillowing vport mapping (for single E-Switch per PF):
-1 - wire
0 - PF (uplink + VF reps)
1 - VF0
2 - VF1
...
n+1 - VFn
This code is subject to change - (SF, multi E-Switch per function, etc),
this patch currently supports single E-Switch per PF.
>
> > + 0xffff);
> > + }
> > for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
> > int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
> > void *match_mask = matcher.mask.buf;
> > --
> > 1.8.3.1
Thursday, March 21, 2019 4:12 PM, Slava Ovsiienko:
> Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the ingress
> rules
> > >
> > > Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
[...]
> > > + flow_dv_translate_source_vport(matcher.mask.buf,
> > > + dev_flow->dv.value.buf,
> > > + priv->representor_id < 0 ?
> > > + priv->representor_id :
> > > + priv->representor_id + 1,
> >
> > The vport of representor_id 0 will be 1?
> > Who owns vport 0?
>
> PF.
> There is the foillowing vport mapping (for single E-Switch per PF):
>
> -1 - wire
Wire, i.e. the uplink representor. indeed it's index is defined by PRM to -1.
> 0 - PF (uplink + VF reps)
I don't understand this part. When you have uplink representor you don't have PF.
Moreover, I would expect the first representor created to have vport_num=0 (w/ name pf0vf0).
Isn't it the case?
> 1 - VF0
> 2 - VF1
> ...
> n+1 - VFn
>
> This code is subject to change - (SF, multi E-Switch per function, etc), this
> patch currently supports single E-Switch per PF.
>
> >
> > > + 0xffff);
> > > + }
> > > for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
> > > int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
> > > void *match_mask = matcher.mask.buf;
> > > --
> > > 1.8.3.1
> -----Original Message-----
> From: Shahaf Shuler
> Sent: Sunday, March 24, 2019 11:14
> To: Slava Ovsiienko <viacheslavo@mellanox.com>; dev@dpdk.org
> Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the ingress
> rules
>
> Thursday, March 21, 2019 4:12 PM, Slava Ovsiienko:
> > Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the
> > ingress rules
> > > >
> > > > Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
>
> [...]
>
> > > > + flow_dv_translate_source_vport(matcher.mask.buf,
> > > > + dev_flow->dv.value.buf,
> > > > + priv->representor_id < 0 ?
> > > > + priv->representor_id :
> > > > + priv->representor_id + 1,
> > >
> > > The vport of representor_id 0 will be 1?
> > > Who owns vport 0?
> >
> > PF.
> > There is the foillowing vport mapping (for single E-Switch per PF):
> >
> > -1 - wire
>
> Wire, i.e. the uplink representor. indeed it's index is defined by PRM to -1.
>
> > 0 - PF (uplink + VF reps)
>
> I don't understand this part. When you have uplink representor you don't
> have PF.
We do. There is PF anyway. In meaning we always have PCI function, which
Is some kind of "container" for representors and also serves as E-Switch manager.
It may contain only "uplink rep" if there is no VF enabled, or may contain the bunch
of uplink and VF reps. This PF has vport zero assigned.
> Moreover, I would expect the first representor created to have vport_num=0
> (w/ name pf0vf0).
> Isn't it the case?
No. Representors do not have dedicated vports, they share the vport zero (PF) instead.
And VFs have dedicated vports.
>
> > 1 - VF0
> > 2 - VF1
> > ...
> > n+1 - VFn
> >
> > This code is subject to change - (SF, multi E-Switch per function,
> > etc), this patch currently supports single E-Switch per PF.
> >
> > >
> > > > + 0xffff);
> > > > + }
> > > > for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
> > > > int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
> > > > void *match_mask = matcher.mask.buf;
> > > > --
> > > > 1.8.3.1
@@ -3095,6 +3095,29 @@ struct field_modify_info modify_tcp[] = {
}
/**
+ * Add source vport match to the specified matcher.
+ *
+ * @param[in, out] matcher
+ * Flow matcher.
+ * @param[in, out] key
+ * Flow matcher value.
+ * @param[in] port
+ * Source vport value to match
+ * @param[in] mask
+ * Mask
+ */
+static void
+flow_dv_translate_source_vport(void *matcher, void *key,
+ int16_t port, uint16_t mask)
+{
+ void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+ void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+
+ MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
+ MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
+}
+
+/**
* Fill the flow with DV spec.
*
* @param[in] dev
@@ -3389,6 +3412,21 @@ struct field_modify_info modify_tcp[] = {
}
dev_flow->dv.actions_n = actions_n;
flow->actions = action_flags;
+ if (attr->ingress && !attr->transfer &&
+ (priv->representor || priv->master)) {
+ /* It was validated - we support unidirections flows only. */
+ assert(!attr->egress);
+ /*
+ * Add matching on source vport index only
+ * for ingress rules in E-Switch configurations.
+ */
+ flow_dv_translate_source_vport(matcher.mask.buf,
+ dev_flow->dv.value.buf,
+ priv->representor_id < 0 ?
+ priv->representor_id :
+ priv->representor_id + 1,
+ 0xffff);
+ }
for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
void *match_mask = matcher.mask.buf;