diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 670d7f7..f66263c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -32,6 +32,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k
 DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e
 DIRS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice
 DIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe
+DIRS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += ipn3ke
 DIRS-$(CONFIG_RTE_LIBRTE_LIO_PMD) += liquidio
 DIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += mlx4
 DIRS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5
diff --git a/drivers/net/ipn3ke/Makefile b/drivers/net/ipn3ke/Makefile
new file mode 100644
index 0000000..03f2145
--- /dev/null
+++ b/drivers/net/ipn3ke/Makefile
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Intel Corporation
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_pmd_ipn3ke.a
+
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+CFLAGS += -O3
+#CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/bus/ifpga
+CFLAGS += -I$(RTE_SDK)/drivers/raw/ifpga_rawdev
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
+LDLIBS += -lrte_bus_pci
+LDLIBS += -lrte_bus_vdev
+
+EXPORT_MAP := rte_pmd_ipn3ke_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-y += ipn3ke_ethdev.c
+SRCS-y += ipn3ke_representor.c
+SRCS-y += ipn3ke_tm.c
+SRCS-y += ipn3ke_flow.c
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c
new file mode 100644
index 0000000..e691f68
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c
@@ -0,0 +1,814 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <stdint.h>
+
+#include <rte_bus_pci.h>
+#include <rte_ethdev.h>
+#include <rte_pci.h>
+#include <rte_malloc.h>
+
+#include <rte_mbuf.h>
+#include <rte_sched.h>
+#include <rte_ethdev_driver.h>
+
+#include <rte_io.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+#include <rte_bus_ifpga.h>
+#include <ifpga_common.h>
+#include <ifpga_logs.h>
+
+#include "ifpga_rawdev_api.h"
+#include "ipn3ke_tm.h"
+#include "ipn3ke_flow.h"
+#include "ipn3ke_logs.h"
+#include "ipn3ke_ethdev.h"
+
+int ipn3ke_afu_logtype;
+
+static const struct rte_afu_uuid afu_uuid_ipn3ke_map[] = {
+	{ MAP_UUID_10G_LOW,  MAP_UUID_10G_HIGH },
+	{ IPN3KE_UUID_10G_LOW, IPN3KE_UUID_10G_HIGH },
+	{ IPN3KE_UUID_25G_LOW, IPN3KE_UUID_25G_HIGH },
+	{ 0, 0 /* sentinel */ },
+};
+
+struct ipn3ke_hw_cap hw_cap;
+
+static int ipn3ke_indirect_read(struct ipn3ke_hw *hw,
+					 uint32_t *rd_data,
+					 uint32_t addr,
+					 uint32_t mac_num,
+					 uint32_t dev_sel,
+					 uint32_t eth_wrapper_sel)
+{
+	uint32_t base_addr;
+	uint32_t i, try_cnt;
+	uint32_t delay = 0xFFFFF;
+	uint64_t indirect_value = 0;
+	volatile void *indirect_addrs = 0;
+	uint64_t target_addr = 0;
+	uint64_t read_data = 0;
+
+	if (mac_num >= hw->port_num)
+		return -1;
+
+	if (eth_wrapper_sel == 0)
+		base_addr = IPN3KE_MAC_CTRL_BASE_0;
+	else if (eth_wrapper_sel == 1)
+		base_addr = IPN3KE_MAC_CTRL_BASE_1;
+	else
+		return -1;
+
+	addr &= 0x3FF;
+	mac_num &= 0x7;
+	mac_num <<= 10;
+	target_addr = addr | mac_num;
+
+	indirect_value = RCMD | target_addr << 32;
+	indirect_addrs = (volatile void *)(hw->hw_addr +
+						(uint32_t)(base_addr | 0x10));
+
+	while (delay != 0)
+		delay--;
+
+	rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
+
+	i = 0;
+	try_cnt = 10;
+	indirect_addrs = (volatile void *)(hw->hw_addr +
+						(uint32_t)(base_addr | 0x18));
+	do {
+		read_data = rte_read64(indirect_addrs);
+		if ((read_data >> 32) == 1)
+			break;
+		i++;
+	} while (i <= try_cnt);
+	if (i > try_cnt)
+		return -1;
+
+	(*rd_data) = rte_le_to_cpu_32(read_data);
+	return 0;
+}
+
+static int ipn3ke_indirect_write(struct ipn3ke_hw *hw,
+					 uint32_t wr_data,
+					 uint32_t addr,
+					 uint32_t mac_num,
+					 uint32_t dev_sel,
+					 uint32_t eth_wrapper_sel)
+{
+	uint32_t base_addr;
+	volatile void *indirect_addrs = 0;
+	uint64_t indirect_value = 0;
+	uint64_t target_addr = 0;
+
+	if (mac_num >= hw->port_num)
+		return -1;
+
+	if (eth_wrapper_sel == 0)
+		base_addr = IPN3KE_MAC_CTRL_BASE_0;
+	else if (eth_wrapper_sel == 1)
+		base_addr = IPN3KE_MAC_CTRL_BASE_1;
+	else
+		return -1;
+
+	addr &= 0x3FF;
+	mac_num &= 0x7;
+	mac_num <<= 10;
+	target_addr = addr | mac_num;
+
+	indirect_value = WCMD | target_addr << 32 | wr_data;
+	indirect_addrs = (volatile void *)(hw->hw_addr +
+					(uint32_t)(base_addr | 0x10));
+
+	rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
+	return 0;
+}
+
+static int ipn3ke_indirect_mac_read(struct ipn3ke_hw *hw,
+						 uint32_t *rd_data,
+						 uint32_t addr,
+						 uint32_t mac_num,
+						 uint32_t eth_wrapper_sel)
+{
+	return ipn3ke_indirect_read(hw,
+				rd_data,
+				addr,
+				mac_num,
+				0,
+				eth_wrapper_sel);
+}
+
+static int ipn3ke_indirect_mac_write(struct ipn3ke_hw *hw,
+						 uint32_t wr_data,
+						 uint32_t addr,
+						 uint32_t mac_num,
+						 uint32_t eth_wrapper_sel)
+{
+	return ipn3ke_indirect_write(hw,
+				wr_data,
+				addr,
+				mac_num,
+				0,
+				eth_wrapper_sel);
+}
+
+#define MAP_PHY_MAC_BASE 0x409000
+#define MAP_FVL_MAC_BASE 0x809000
+static int map_indirect_mac_read(struct ipn3ke_hw *hw,
+					 uint32_t *rd_data,
+					 uint32_t addr,
+					 uint32_t mac_num,
+					 uint32_t eth_wrapper_sel)
+{
+	uint32_t base_addr;
+
+	base_addr = MAP_PHY_MAC_BASE +
+		0x400000 * eth_wrapper_sel +
+		0x1000 * mac_num +
+		(addr << 4);
+
+	(*rd_data) = IPN3KE_READ_REG(hw, base_addr);
+
+	return 0;
+}
+static int map_indirect_mac_write(struct ipn3ke_hw *hw,
+					 uint32_t wr_data,
+					 uint32_t addr,
+					 uint32_t mac_num,
+					 uint32_t eth_wrapper_sel)
+{
+	uint32_t base_addr;
+
+	base_addr = MAP_PHY_MAC_BASE +
+		0x400000 * eth_wrapper_sel +
+		0x1000 * mac_num +
+		(addr << 4);
+
+	IPN3KE_WRITE_REG(hw, base_addr, wr_data);
+
+	return 0;
+}
+
+static int
+ipn3ke_hw_cap_init(struct ipn3ke_hw *hw)
+{
+	hw_cap.version_number = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0), 0, 0xFFFF);
+	hw_cap.capability_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x8), 0, 0xFFFFFFFF);
+	hw_cap.status_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x10), 0, 0xFFFFFFFF);
+	hw_cap.control_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x18), 0, 0xFFFFFFFF);
+	hw_cap.classify_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x20), 0, 0xFFFFFFFF);
+	hw_cap.classy_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x24), 0, 0xFFFF);
+	hw_cap.policer_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x28), 0, 0xFFFFFFFF);
+	hw_cap.policer_entry_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x2C), 0, 0xFFFF);
+	hw_cap.rss_key_array_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x30), 0, 0xFFFFFFFF);
+	hw_cap.rss_key_entry_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x34), 0, 0xFFFF);
+	hw_cap.rss_indirection_table_array_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x38), 0, 0xFFFFFFFF);
+	hw_cap.rss_indirection_table_entry_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x3C), 0, 0xFFFF);
+	hw_cap.dmac_map_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x40), 0, 0xFFFFFFFF);
+	hw_cap.dmac_map_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x44), 0, 0xFFFF);
+	hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x48), 0, 0xFFFFFFFF);
+	hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x4C), 0, 0xFFFF);
+	hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x50), 0, 0xFFFFFFFF);
+	hw_cap.ccb_entry_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x54), 0, 0xFFFF);
+	hw_cap.qos_offset = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x58), 0, 0xFFFFFFFF);
+	hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw,
+			(IPN3KE_HW_BASE + 0x5C), 0, 0xFFFF);
+
+	hw_cap.num_rx_flow = IPN3KE_MASK_READ_REG(hw,
+			IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
+			0, 0xFFFF);
+	hw_cap.num_rss_blocks = IPN3KE_MASK_READ_REG(hw,
+			IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
+			4, 0xFFFF);
+	hw_cap.num_dmac_map = IPN3KE_MASK_READ_REG(hw,
+			IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
+			8, 0xFFFF);
+	hw_cap.num_tx_flow = IPN3KE_MASK_READ_REG(hw,
+			IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
+			0xC, 0xFFFF);
+	hw_cap.num_smac_map = IPN3KE_MASK_READ_REG(hw,
+			IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
+			0x10, 0xFFFF);
+
+	hw_cap.link_speed_mbps = IPN3KE_MASK_READ_REG(hw,
+			IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET,
+			0, 0xFFFFF);
+
+	return 0;
+}
+
+static int
+ipn3ke_hw_init_base(struct rte_afu_device *afu_dev,
+	struct ipn3ke_hw *hw)
+{
+	struct rte_rawdev *rawdev;
+	int ret;
+	int i;
+	uint32_t val;
+
+	rawdev  = afu_dev->rawdev;
+
+	hw->afu_id.uuid.uuid_low = afu_dev->id.uuid.uuid_low;
+	hw->afu_id.uuid.uuid_high = afu_dev->id.uuid.uuid_high;
+	hw->afu_id.port = afu_dev->id.port;
+	hw->hw_addr = (uint8_t *)(afu_dev->mem_resource[0].addr);
+	if ((afu_dev->id.uuid.uuid_low == MAP_UUID_10G_LOW) &&
+		(afu_dev->id.uuid.uuid_high == MAP_UUID_10G_HIGH)) {
+		hw->f_mac_read = map_indirect_mac_read;
+		hw->f_mac_write = map_indirect_mac_write;
+	} else {
+		hw->f_mac_read = ipn3ke_indirect_mac_read;
+		hw->f_mac_write = ipn3ke_indirect_mac_write;
+	}
+	hw->rawdev = rawdev;
+	rawdev->dev_ops->attr_get(rawdev,
+				"retimer_info",
+				(uint64_t *)&hw->retimer);
+	hw->port_num = hw->retimer.port_num;
+
+	/* Enable inter connect channel */
+	for (i = 0; i < hw->port_num; i++) {
+		/* Enable the TX path */
+		val = 0;
+		val &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_PACKET_CONTROL,
+				i,
+				1);
+
+		/* Disables source address override */
+		val = 0;
+		val &= IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE,
+				i,
+				1);
+
+		/* Enable the RX path */
+		val = 0;
+		val &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_RX_TRANSFER_CONTROL,
+				i,
+				1);
+
+		/* Clear all TX statistics counters */
+		val = 1;
+		val &= IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_STATS_CLR,
+				i,
+				1);
+
+		/* Clear all RX statistics counters */
+		val = 1;
+		val &= IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_RX_STATS_CLR,
+				i,
+				1);
+	}
+
+	ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);
+	if (ret)
+		IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d",
+		ret);
+
+	hw->tm_hw_enable = 0;
+	hw->flow_hw_enable = 0;
+
+	hw->acc_tm = 0;
+	hw->acc_flow = 0;
+
+	return 0;
+}
+
+static int
+ipn3ke_hw_init_vbng(struct rte_afu_device *afu_dev,
+	struct ipn3ke_hw *hw)
+{
+	struct rte_rawdev *rawdev;
+	int ret;
+	int i;
+	uint32_t val;
+
+	rawdev  = afu_dev->rawdev;
+
+	hw->afu_id.uuid.uuid_low = afu_dev->id.uuid.uuid_low;
+	hw->afu_id.uuid.uuid_high = afu_dev->id.uuid.uuid_high;
+	hw->afu_id.port = afu_dev->id.port;
+	hw->hw_addr = (uint8_t *)(afu_dev->mem_resource[0].addr);
+	if ((afu_dev->id.uuid.uuid_low == MAP_UUID_10G_LOW) &&
+		(afu_dev->id.uuid.uuid_high == MAP_UUID_10G_HIGH)) {
+		hw->f_mac_read = map_indirect_mac_read;
+		hw->f_mac_write = map_indirect_mac_write;
+	} else {
+		hw->f_mac_read = ipn3ke_indirect_mac_read;
+		hw->f_mac_write = ipn3ke_indirect_mac_write;
+	}
+	hw->rawdev = rawdev;
+	rawdev->dev_ops->attr_get(rawdev,
+				"retimer_info",
+				(uint64_t *)&hw->retimer);
+	hw->port_num = hw->retimer.port_num;
+
+	ipn3ke_hw_cap_init(hw);
+	printf("UPL_version is 0x%x\n", IPN3KE_READ_REG(hw, 0));
+
+	/* Reset FPGA IP */
+	IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);
+	IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);
+
+	/* Enable inter connect channel */
+	for (i = 0; i < hw->port_num; i++) {
+		/* Enable the TX path */
+		val = 0;
+		val &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_PACKET_CONTROL,
+				i,
+				1);
+
+		/* Disables source address override */
+		val = 0;
+		val &= IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE,
+				i,
+				1);
+
+		/* Enable the RX path */
+		val = 0;
+		val &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_RX_TRANSFER_CONTROL,
+				i,
+				1);
+
+		/* Clear all TX statistics counters */
+		val = 1;
+		val &= IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_STATS_CLR,
+				i,
+				1);
+
+		/* Clear all RX statistics counters */
+		val = 1;
+		val &= IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_RX_STATS_CLR,
+				i,
+				1);
+	}
+
+	ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);
+	if (ret)
+		IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d",
+		ret);
+
+	ret = ipn3ke_hw_tm_init(hw);
+	if (ret)
+		return ret;
+	hw->tm_hw_enable = 1;
+
+	ret = ipn3ke_flow_init(hw);
+	if (ret)
+		return ret;
+	hw->flow_hw_enable = 1;
+
+	hw->acc_tm = 0;
+	hw->acc_flow = 0;
+
+	return 0;
+}
+
+static void
+ipn3ke_hw_uninit(struct ipn3ke_hw *hw)
+{
+	int i;
+	uint32_t val;
+
+	for (i = 0; i < hw->port_num; i++) {
+		/* Disable the TX path */
+		val = 1;
+		val &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_PACKET_CONTROL,
+				0,
+				1);
+
+		/* Disable the RX path */
+		val = 1;
+		val &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_RX_TRANSFER_CONTROL,
+				0,
+				1);
+
+		/* Clear all TX statistics counters */
+		val = 1;
+		val &= IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_TX_STATS_CLR,
+				0,
+				1);
+
+		/* Clear all RX statistics counters */
+		val = 1;
+		val &= IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK;
+		(*hw->f_mac_write)(hw,
+				val,
+				IPN3KE_MAC_RX_STATS_CLR,
+				0,
+				1);
+	}
+}
+
+RTE_INIT(ipn3ke_afu_init_log);
+static void
+ipn3ke_afu_init_log(void)
+{
+	ipn3ke_afu_logtype = rte_log_register("driver.afu.ipn3ke");
+	if (ipn3ke_afu_logtype >= 0)
+		rte_log_set_level(ipn3ke_afu_logtype, RTE_LOG_NOTICE);
+}
+
+static int ipn3ke_vswitch_probe(struct rte_afu_device *afu_dev)
+{
+	char name[RTE_ETH_NAME_MAX_LEN];
+	struct ipn3ke_hw *hw;
+	int i, retval;
+
+	/* check if the AFU device has been probed already */
+	/* allocate shared mcp_vswitch structure */
+	if (!afu_dev->shared.data) {
+		snprintf(name, sizeof(name), "net_%s_hw",
+			afu_dev->device.name);
+		hw = rte_zmalloc_socket(name,
+					sizeof(struct ipn3ke_hw),
+					RTE_CACHE_LINE_SIZE,
+					afu_dev->device.numa_node);
+		if (!hw) {
+			IPN3KE_AFU_PMD_LOG(ERR,
+				"failed to allocate hardwart data");
+				retval = -ENOMEM;
+				return -ENOMEM;
+		}
+		afu_dev->shared.data = hw;
+
+		rte_spinlock_init(&afu_dev->shared.lock);
+	} else
+		hw = (struct ipn3ke_hw *)afu_dev->shared.data;
+
+#if IPN3KE_HW_BASE_ENABLE
+	retval = ipn3ke_hw_init_base(afu_dev, hw);
+	if (retval)
+		return retval;
+#endif
+
+	retval = ipn3ke_hw_init_vbng(afu_dev, hw);
+	if (retval)
+		return retval;
+
+	/* probe representor ports */
+	for (i = 0; i < hw->port_num; i++) {
+		struct ipn3ke_rpst rpst = {
+			.port_id = i,
+			.switch_domain_id = hw->switch_domain_id,
+			.hw = hw
+		};
+
+		/* representor port net_bdf_port */
+		snprintf(name, sizeof(name), "net_%s_representor_%d",
+			afu_dev->device.name, i);
+
+		retval = rte_eth_dev_create(&afu_dev->device, name,
+			sizeof(struct ipn3ke_rpst), NULL, NULL,
+			ipn3ke_rpst_init, &rpst);
+
+		if (retval)
+			IPN3KE_AFU_PMD_LOG(ERR, "failed to create ipn3ke "
+				"representor %s.", name);
+	}
+
+	return 0;
+}
+
+static int ipn3ke_vswitch_remove(struct rte_afu_device *afu_dev)
+{
+	char name[RTE_ETH_NAME_MAX_LEN];
+	struct ipn3ke_hw *hw;
+	struct rte_eth_dev *ethdev;
+	int i, ret;
+
+	hw = (struct ipn3ke_hw *)afu_dev->shared.data;
+
+	/* remove representor ports */
+	for (i = 0; i < hw->port_num; i++) {
+		/* representor port net_bdf_port */
+		snprintf(name, sizeof(name), "net_%s_representor_%d",
+			afu_dev->device.name, i);
+
+		ethdev = rte_eth_dev_allocated(afu_dev->device.name);
+		if (!ethdev)
+			return -ENODEV;
+
+		rte_eth_dev_destroy(ethdev, ipn3ke_rpst_uninit);
+	}
+
+	ret = rte_eth_switch_domain_free(hw->switch_domain_id);
+	if (ret)
+		IPN3KE_AFU_PMD_LOG(WARNING,
+							"failed to free switch domain: %d",
+							ret);
+
+	/* flow uninit*/
+
+	ipn3ke_hw_uninit(hw);
+
+	return 0;
+}
+
+static struct rte_afu_driver afu_ipn3ke_driver = {
+	.id_table = afu_uuid_ipn3ke_map,
+	.probe = ipn3ke_vswitch_probe,
+	.remove = ipn3ke_vswitch_remove,
+};
+
+RTE_PMD_REGISTER_AFU(net_ipn3ke_afu, afu_ipn3ke_driver);
+RTE_PMD_REGISTER_AFU_ALIAS(net_ipn3ke_afu, afu_dev);
+RTE_PMD_REGISTER_PARAM_STRING(net_ipn3ke_afu,
+	"bdf=<string> "
+	"port=<int> "
+	"uudi_high=<int64> "
+	"uuid_low=<int64> "
+	"path=<string> "
+	"pr_enable=<int>"
+	"debug=<int>");
+
+static const char * const valid_args[] = {
+#define IPN3KE_AFU_NAME         "afu"
+		IPN3KE_AFU_NAME,
+#define IPN3KE_FPGA_ACCELERATION_LIST     "fpga_acc"
+		IPN3KE_FPGA_ACCELERATION_LIST,
+#define IPN3KE_I40E_PF_LIST     "i40e_pf"
+		IPN3KE_I40E_PF_LIST,
+		NULL
+};
+static int
+ipn3ke_cfg_parse_acc_list(const char *afu_name,
+const char *acc_list_name)
+{
+	struct rte_afu_device *afu_dev;
+	struct ipn3ke_hw *hw;
+	const char *p_source;
+	char *p_start;
+	char name[RTE_ETH_NAME_MAX_LEN];
+
+	afu_dev = rte_ifpga_find_afu_by_name(afu_name);
+	if (!afu_dev)
+		return -1;
+	hw = (struct ipn3ke_hw *)afu_dev->shared.data;
+	if (!hw)
+		return -1;
+
+	p_source = acc_list_name;
+	while (*p_source) {
+		while ((*p_source == '{') || (*p_source == '|'))
+			p_source++;
+		p_start = name;
+		while ((*p_source != '|') && (*p_source != '}'))
+			*p_start++ = *p_source++;
+		*p_start = 0;
+		if (!strcmp(name, "tm") && hw->tm_hw_enable)
+			hw->acc_tm = 1;
+
+		if (!strcmp(name, "flow") && hw->flow_hw_enable)
+			hw->acc_flow = 1;
+
+		if (*p_source == '}')
+			return 0;
+	}
+
+	return 0;
+}
+
+static int
+ipn3ke_cfg_parse_i40e_pf_ethdev(const char *afu_name,
+const char *pf_name)
+{
+	struct rte_eth_dev *i40e_eth, *rpst_eth;
+	struct rte_afu_device *afu_dev;
+	struct ipn3ke_rpst *rpst;
+	struct ipn3ke_hw *hw;
+	const char *p_source;
+	char *p_start;
+	char name[RTE_ETH_NAME_MAX_LEN];
+	uint16_t port_id;
+	int i;
+	int ret = -1;
+
+	afu_dev = rte_ifpga_find_afu_by_name(afu_name);
+	if (!afu_dev)
+		return -1;
+	hw = (struct ipn3ke_hw *)afu_dev->shared.data;
+	if (!hw)
+		return -1;
+
+	p_source = pf_name;
+	for (i = 0; i < hw->port_num; i++) {
+		snprintf(name, sizeof(name), "net_%s_representor_%d",
+			afu_name, i);
+		ret = rte_eth_dev_get_port_by_name(name, &port_id);
+		rpst_eth = &rte_eth_devices[port_id];
+		rpst = IPN3KE_DEV_PRIVATE_TO_RPST(rpst_eth);
+
+		while ((*p_source == '{') || (*p_source == '|'))
+			p_source++;
+		p_start = name;
+		while ((*p_source != '|') && (*p_source != '}'))
+			*p_start++ = *p_source++;
+		*p_start = 0;
+
+		ret = rte_eth_dev_get_port_by_name(name, &port_id);
+		i40e_eth = &rte_eth_devices[port_id];
+
+		rpst->i40e_pf_eth = i40e_eth;
+		rpst->i40e_pf_eth_port_id = port_id;
+
+		if ((*p_source == '}') || !(*p_source))
+			break;
+	}
+
+	return 0;
+}
+static int
+ipn3ke_cfg_probe(struct rte_vdev_device *dev)
+{
+	struct rte_devargs *devargs;
+	struct rte_kvargs *kvlist = NULL;
+	char *afu_name = NULL;
+	char *acc_name = NULL;
+	char *pf_name = NULL;
+	int ret = -1;
+
+	devargs = dev->device.devargs;
+
+	kvlist = rte_kvargs_parse(devargs->args, valid_args);
+	if (!kvlist) {
+		IPN3KE_AFU_PMD_LOG(ERR, "error when parsing param");
+		goto end;
+	}
+
+	if (rte_kvargs_count(kvlist, IPN3KE_AFU_NAME) == 1) {
+		if (rte_kvargs_process(kvlist, IPN3KE_AFU_NAME,
+				       &rte_ifpga_get_string_arg,
+				       &afu_name) < 0) {
+			IPN3KE_AFU_PMD_ERR("error to parse %s",
+				     IPN3KE_AFU_NAME);
+			goto end;
+		}
+	} else {
+		IPN3KE_AFU_PMD_ERR("arg %s is mandatory for ipn3ke",
+			  IPN3KE_AFU_NAME);
+		goto end;
+	}
+
+	if (rte_kvargs_count(kvlist, IPN3KE_FPGA_ACCELERATION_LIST) == 1) {
+		if (rte_kvargs_process(kvlist, IPN3KE_FPGA_ACCELERATION_LIST,
+				       &rte_ifpga_get_string_arg,
+				       &acc_name) < 0) {
+			IPN3KE_AFU_PMD_ERR("error to parse %s",
+				     IPN3KE_FPGA_ACCELERATION_LIST);
+			goto end;
+		}
+		ret = ipn3ke_cfg_parse_acc_list(afu_name, acc_name);
+		if (ret)
+			goto end;
+	} else {
+		IPN3KE_AFU_PMD_INFO("arg %s is optional for ipn3ke, using i40e acc",
+			  IPN3KE_FPGA_ACCELERATION_LIST);
+	}
+
+	if (rte_kvargs_count(kvlist, IPN3KE_I40E_PF_LIST) == 1) {
+		if (rte_kvargs_process(kvlist, IPN3KE_I40E_PF_LIST,
+				       &rte_ifpga_get_string_arg,
+				       &pf_name) < 0) {
+			IPN3KE_AFU_PMD_ERR("error to parse %s",
+				     IPN3KE_I40E_PF_LIST);
+			goto end;
+		}
+		ret = ipn3ke_cfg_parse_i40e_pf_ethdev(afu_name, pf_name);
+		if (ret)
+			goto end;
+	} else {
+		IPN3KE_AFU_PMD_ERR("arg %s is mandatory for ipn3ke",
+			  IPN3KE_I40E_PF_LIST);
+		goto end;
+	}
+
+end:
+	if (kvlist)
+		rte_kvargs_free(kvlist);
+
+	return ret;
+}
+
+static int
+ipn3ke_cfg_remove(struct rte_vdev_device *vdev)
+{
+	IPN3KE_AFU_PMD_INFO("Remove ipn3ke_cfg %p",
+		vdev);
+
+	return 0;
+}
+
+static struct rte_vdev_driver ipn3ke_cfg_driver = {
+	.probe = ipn3ke_cfg_probe,
+	.remove = ipn3ke_cfg_remove,
+};
+
+RTE_PMD_REGISTER_VDEV(ipn3ke_cfg, ipn3ke_cfg_driver);
+RTE_PMD_REGISTER_ALIAS(ipn3ke_cfg, ipn3ke_cfg);
+RTE_PMD_REGISTER_PARAM_STRING(ipn3ke_cfg,
+	"afu=<string> "
+	"fpga_acc=<string>"
+	"i40e=<string>");
+
diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h
new file mode 100644
index 0000000..d5cc6f4
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h
@@ -0,0 +1,742 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _IPN3KE_ETHDEV_H_
+#define _IPN3KE_ETHDEV_H_
+
+#include <rte_bus_ifpga.h>
+
+/** Set a bit in the uint32 variable */
+#define IPN3KE_BIT_SET(var, pos) \
+	((var) |= ((uint32_t)1 << ((pos))))
+
+/** Reset the bit in the variable */
+#define IPN3KE_BIT_RESET(var, pos) \
+	((var) &= ~((uint32_t)1 << ((pos))))
+
+/** Check the bit is set in the variable */
+#define IPN3KE_BIT_ISSET(var, pos) \
+	(((var) & ((uint32_t)1 << ((pos)))) ? 1 : 0)
+
+struct ipn3ke_hw;
+
+#define IPN3KE_HW_BASE               0x4000000
+
+#define IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.capability_registers_block_offset)
+
+#define IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.status_registers_block_offset)
+
+#define IPN3KE_CTRL_RESET \
+	(IPN3KE_HW_BASE + hw_cap.control_registers_block_offset)
+
+#define IPN3KE_CTRL_MTU \
+	(IPN3KE_HW_BASE + hw_cap.control_registers_block_offset + 4)
+
+#define IPN3KE_CLASSIFY_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.classify_offset)
+
+#define IPN3KE_POLICER_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.policer_offset)
+
+#define IPN3KE_RSS_KEY_ARRAY_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.rss_key_array_offset)
+
+#define IPN3KE_RSS_INDIRECTION_TABLE_ARRAY_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.rss_indirection_table_array_offset)
+
+#define IPN3KE_DMAC_MAP_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.dmac_map_offset)
+
+#define IPN3KE_QM_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.qm_offset)
+
+#define IPN3KE_CCB_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.ccb_offset)
+
+#define IPN3KE_QOS_OFFSET \
+	(IPN3KE_HW_BASE + hw_cap.qos_offset)
+
+struct ipn3ke_hw_cap {
+	uint32_t version_number;
+	uint32_t capability_registers_block_offset;
+	uint32_t status_registers_block_offset;
+	uint32_t control_registers_block_offset;
+	uint32_t classify_offset;
+	uint32_t classy_size;
+	uint32_t policer_offset;
+	uint32_t policer_entry_size;
+	uint32_t rss_key_array_offset;
+	uint32_t rss_key_entry_size;
+	uint32_t rss_indirection_table_array_offset;
+	uint32_t rss_indirection_table_entry_size;
+	uint32_t dmac_map_offset;
+	uint32_t dmac_map_size;
+	uint32_t qm_offset;
+	uint32_t qm_size;
+	uint32_t ccb_offset;
+	uint32_t ccb_entry_size;
+	uint32_t qos_offset;
+	uint32_t qos_size;
+
+	uint32_t num_rx_flow;    /* Default: 64K */
+	uint32_t num_rss_blocks; /* Default: 512 */
+	uint32_t num_dmac_map;   /* Default: 1K */
+	uint32_t num_tx_flow;    /* Default: 64K */
+	uint32_t num_smac_map;   /* Default: 1K */
+
+	uint32_t link_speed_mbps;
+};
+
+/**
+ * Strucute to store private data for each representor instance
+ */
+struct ipn3ke_rpst {
+	TAILQ_ENTRY(ipn3ke_rpst) next;       /**< Next in device list. */
+	uint16_t switch_domain_id;
+	/**< Switch ID */
+	uint16_t port_id;
+	/**< Port ID */
+	struct ipn3ke_hw *hw;
+	struct rte_eth_dev *i40e_pf_eth;
+	uint16_t i40e_pf_eth_port_id;
+	struct rte_eth_link ori_linfo;
+	struct ipn3ke_tm_internals tm;
+	/**< Private data store of assocaiated physical function */
+	struct ether_addr mac_addr;
+};
+
+/* UUID IDs */
+#define MAP_UUID_10G_LOW                0xffffffffffffffff
+#define MAP_UUID_10G_HIGH               0xffffffffffffffff
+#define IPN3KE_UUID_10G_LOW             0xc000c9660d824272
+#define IPN3KE_UUID_10G_HIGH            0x9aeffe5f84570612
+#define IPN3KE_UUID_25G_LOW             0xb7d9bac566bfbc80
+#define IPN3KE_UUID_25G_HIGH            0xb07bac1aeef54d67
+
+#define IPN3KE_AFU_BUF_SIZE_MIN         1024
+#define IPN3KE_AFU_FRAME_SIZE_MAX       9728
+
+#define IPN3KE_RAWDEV_ATTR_LEN_MAX      (64)
+
+typedef int (*ipn3ke_indirect_mac_read_t)(struct ipn3ke_hw *hw,
+				 uint32_t *rd_data,
+				 uint32_t addr,
+				 uint32_t mac_num,
+				 uint32_t eth_wrapper_sel);
+
+typedef int (*ipn3ke_indirect_mac_write_t)(struct ipn3ke_hw *hw,
+				 uint32_t wr_data,
+				 uint32_t addr,
+				 uint32_t mac_num,
+				 uint32_t eth_wrapper_sel);
+
+struct ipn3ke_hw {
+	struct rte_eth_dev *eth_dev;
+
+	/* afu info */
+	struct rte_afu_id afu_id;
+	struct rte_rawdev *rawdev;
+
+	struct ifpga_rawdevg_retimer_info retimer;
+
+	uint16_t switch_domain_id;
+	uint16_t port_num;
+
+	uint32_t tm_hw_enable;
+	uint32_t flow_hw_enable;
+
+	uint32_t acc_tm;
+	uint32_t acc_flow;
+
+	struct ipn3ke_flow_list flow_list;
+	uint32_t flow_max_entries;
+	uint32_t flow_num_entries;
+
+	struct ipn3ke_tm_node *nodes;
+	struct ipn3ke_tm_node *port_nodes;
+	struct ipn3ke_tm_node *vt_nodes;
+	struct ipn3ke_tm_node *cos_nodes;
+
+	struct ipn3ke_tm_tdrop_profile *tdrop_profile;
+	uint32_t tdrop_profile_num;
+
+	uint32_t ccb_status;
+	uint32_t ccb_seg_free;
+	uint32_t ccb_seg_num;
+	uint32_t ccb_seg_k;
+
+	/**< MAC Register read */
+	ipn3ke_indirect_mac_read_t f_mac_read;
+	/**< MAC Register write */
+	ipn3ke_indirect_mac_write_t f_mac_write;
+
+	uint8_t *hw_addr;
+};
+
+/**
+ * @internal
+ * Helper macro for drivers that need to convert to struct rte_afu_device.
+ */
+#define RTE_DEV_TO_AFU(ptr) \
+	container_of(ptr, struct rte_afu_device, device)
+
+#define RTE_DEV_TO_AFU_CONST(ptr) \
+	container_of(ptr, const struct rte_afu_device, device)
+
+#define RTE_ETH_DEV_TO_AFU(eth_dev) \
+	RTE_DEV_TO_AFU((eth_dev)->device)
+
+/**
+ * PCIe MMIO Access
+ */
+
+#define IPN3KE_PCI_REG(reg)    rte_read32(reg)
+#define IPN3KE_PCI_REG_ADDR(a, reg) \
+	((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
+static inline uint32_t ipn3ke_read_addr(volatile void *addr)
+{
+	return rte_le_to_cpu_32(IPN3KE_PCI_REG(addr));
+}
+
+#define WCMD 0x8000000000000000
+#define RCMD 0x4000000000000000
+#define UPL_BASE 0x10000
+static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw,
+		uint32_t addr)
+{
+	uint64_t word_offset = 0;
+	uint64_t read_data = 0;
+	uint64_t indirect_value = 0;
+	volatile void *indirect_addrs = 0;
+
+	word_offset = (addr & 0x1FFFFFF) >> 2;
+	indirect_value = RCMD | word_offset << 32;
+	indirect_addrs = (volatile void *)(hw->hw_addr +
+						(uint32_t)(UPL_BASE | 0x10));
+
+	usleep(10);
+
+	rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
+
+	indirect_addrs = (volatile void *)(hw->hw_addr +
+						(uint32_t)(UPL_BASE | 0x18));
+	while ((read_data >> 32) != 1)
+		read_data = rte_read64(indirect_addrs);
+
+	return rte_le_to_cpu_32(read_data);
+}
+
+static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,
+		uint32_t addr, uint32_t value)
+{
+	uint64_t word_offset = 0;
+	uint64_t indirect_value = 0;
+	volatile void *indirect_addrs = 0;
+
+	word_offset = (addr & 0x1FFFFFF) >> 2;
+	indirect_value = WCMD | word_offset << 32 | value;
+	indirect_addrs = (volatile void *)(hw->hw_addr +
+						(uint32_t)(UPL_BASE | 0x10));
+
+	rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
+	usleep(10);
+}
+
+#define IPN3KE_PCI_REG_WRITE(reg, value) \
+	rte_write32((rte_cpu_to_le_32(value)), reg)
+
+#define IPN3KE_PCI_REG_WRITE_RELAXED(reg, value) \
+	rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
+
+#define IPN3KE_READ_REG(hw, reg) \
+	_ipn3ke_indrct_read((hw), (reg))
+
+#define IPN3KE_WRITE_REG(hw, reg, value) \
+	_ipn3ke_indrct_write((hw), (reg), (value))
+
+#define IPN3KE_MASK_READ_REG(hw, reg, x, mask) \
+	((mask) & IPN3KE_READ_REG((hw), ((reg) + (0x4 * (x)))))
+
+#define IPN3KE_MASK_WRITE_REG(hw, reg, x, value, mask) \
+	IPN3KE_WRITE_REG((hw), ((reg) + (0x4 * (x))), ((mask) & (value)))
+
+#define IPN3KE_DEV_PRIVATE_TO_HW(dev) \
+	(((struct ipn3ke_rpst *)(dev)->data->dev_private)->hw)
+
+#define IPN3KE_DEV_PRIVATE_TO_RPST(dev) \
+	((struct ipn3ke_rpst *)(dev)->data->dev_private)
+
+#define IPN3KE_DEV_PRIVATE_TO_TM(dev) \
+	(&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm))
+
+/* Byte address of IPN3KE internal module */
+#define IPN3KE_TM_VERSION                     (IPN3KE_QM_OFFSET + 0x0000)
+#define IPN3KE_TM_SCRATCH                     (IPN3KE_QM_OFFSET + 0x0004)
+#define IPN3KE_TM_STATUS                      (IPN3KE_QM_OFFSET + 0x0008)
+#define IPN3KE_TM_MISC_STATUS                 (IPN3KE_QM_OFFSET + 0x0010)
+#define IPN3KE_TM_MISC_WARNING_0              (IPN3KE_QM_OFFSET + 0x0040)
+#define IPN3KE_TM_MISC_MON_0                  (IPN3KE_QM_OFFSET + 0x0048)
+#define IPN3KE_TM_MISC_FATAL_0                (IPN3KE_QM_OFFSET + 0x0050)
+#define IPN3KE_TM_BW_MON_CTRL_1               (IPN3KE_QM_OFFSET + 0x0080)
+#define IPN3KE_TM_BW_MON_CTRL_2               (IPN3KE_QM_OFFSET + 0x0084)
+#define IPN3KE_TM_BW_MON_RATE                 (IPN3KE_QM_OFFSET + 0x0088)
+#define IPN3KE_TM_STATS_CTRL                  (IPN3KE_QM_OFFSET + 0x0100)
+#define IPN3KE_TM_STATS_DATA_0                (IPN3KE_QM_OFFSET + 0x0110)
+#define IPN3KE_TM_STATS_DATA_1                (IPN3KE_QM_OFFSET + 0x0114)
+#define IPN3KE_QM_UID_CONFIG_CTRL             (IPN3KE_QM_OFFSET + 0x0200)
+#define IPN3KE_QM_UID_CONFIG_DATA             (IPN3KE_QM_OFFSET + 0x0204)
+
+#define IPN3KE_BM_VERSION                     (IPN3KE_QM_OFFSET + 0x4000)
+#define IPN3KE_BM_STATUS                      (IPN3KE_QM_OFFSET + 0x4008)
+#define IPN3KE_BM_STORE_CTRL                  (IPN3KE_QM_OFFSET + 0x4010)
+#define IPN3KE_BM_STORE_STATUS                (IPN3KE_QM_OFFSET + 0x4018)
+#define IPN3KE_BM_STORE_MON                   (IPN3KE_QM_OFFSET + 0x4028)
+#define IPN3KE_BM_WARNING_0                   (IPN3KE_QM_OFFSET + 0x4040)
+#define IPN3KE_BM_MON_0                       (IPN3KE_QM_OFFSET + 0x4048)
+#define IPN3KE_BM_FATAL_0                     (IPN3KE_QM_OFFSET + 0x4050)
+#define IPN3KE_BM_DRAM_ACCESS_CTRL            (IPN3KE_QM_OFFSET + 0x4100)
+#define IPN3KE_BM_DRAM_ACCESS_DATA_0          (IPN3KE_QM_OFFSET + 0x4120)
+#define IPN3KE_BM_DRAM_ACCESS_DATA_1          (IPN3KE_QM_OFFSET + 0x4124)
+#define IPN3KE_BM_DRAM_ACCESS_DATA_2          (IPN3KE_QM_OFFSET + 0x4128)
+#define IPN3KE_BM_DRAM_ACCESS_DATA_3          (IPN3KE_QM_OFFSET + 0x412C)
+#define IPN3KE_BM_DRAM_ACCESS_DATA_4          (IPN3KE_QM_OFFSET + 0x4130)
+#define IPN3KE_BM_DRAM_ACCESS_DATA_5          (IPN3KE_QM_OFFSET + 0x4134)
+#define IPN3KE_BM_DRAM_ACCESS_DATA_6          (IPN3KE_QM_OFFSET + 0x4138)
+
+#define IPN3KE_QM_VERSION                     (IPN3KE_QM_OFFSET + 0x8000)
+#define IPN3KE_QM_STATUS                      (IPN3KE_QM_OFFSET + 0x8008)
+#define IPN3KE_QM_LL_TABLE_MON                (IPN3KE_QM_OFFSET + 0x8018)
+#define IPN3KE_QM_WARNING_0                   (IPN3KE_QM_OFFSET + 0x8040)
+#define IPN3KE_QM_MON_0                       (IPN3KE_QM_OFFSET + 0x8048)
+#define IPN3KE_QM_FATAL_0                     (IPN3KE_QM_OFFSET + 0x8050)
+#define IPN3KE_QM_FATAL_1                     (IPN3KE_QM_OFFSET + 0x8054)
+#define IPN3KE_LL_TABLE_ACCESS_CTRL           (IPN3KE_QM_OFFSET + 0x8100)
+#define IPN3KE_LL_TABLE_ACCESS_DATA_0         (IPN3KE_QM_OFFSET + 0x8110)
+#define IPN3KE_LL_TABLE_ACCESS_DATA_1         (IPN3KE_QM_OFFSET + 0x8114)
+
+#define IPN3KE_CCB_ERROR                      (IPN3KE_CCB_OFFSET + 0x0008)
+#define IPN3KE_CCB_NSEGFREE                   (IPN3KE_CCB_OFFSET + 0x200000)
+#define IPN3KE_CCB_NSEGFREE_MASK               0x3FFFFF
+#define IPN3KE_CCB_PSEGMAX_COEF               (IPN3KE_CCB_OFFSET + 0x200008)
+#define IPN3KE_CCB_PSEGMAX_COEF_MASK           0xFFFFF
+#define IPN3KE_CCB_NSEG_P                     (IPN3KE_CCB_OFFSET + 0x200080)
+#define IPN3KE_CCB_NSEG_MASK                   0x3FFFFF
+#define IPN3KE_CCB_QPROFILE_Q                 (IPN3KE_CCB_OFFSET + 0x240000)
+#define IPN3KE_CCB_QPROFILE_MASK               0x7FF
+#define IPN3KE_CCB_PROFILE_P                  (IPN3KE_CCB_OFFSET + 0x280000)
+#define IPN3KE_CCB_PROFILE_MASK                0x1FFFFFF
+#define IPN3KE_CCB_PROFILE_MS                 (IPN3KE_CCB_OFFSET + 0xC)
+#define IPN3KE_CCB_PROFILE_MS_MASK             0x1FFFFFF
+#define IPN3KE_CCB_LR_LB_DBG_CTRL             (IPN3KE_CCB_OFFSET + 0x2C0000)
+#define IPN3KE_CCB_LR_LB_DBG_DONE             (IPN3KE_CCB_OFFSET + 0x2C0004)
+#define IPN3KE_CCB_LR_LB_DBG_RDATA            (IPN3KE_CCB_OFFSET + 0x2C000C)
+
+#define IPN3KE_QOS_MAP_L1_X                   (IPN3KE_QOS_OFFSET + 0x000000)
+#define IPN3KE_QOS_MAP_L1_MASK                 0x1FFF
+#define IPN3KE_QOS_MAP_L2_X                   (IPN3KE_QOS_OFFSET + 0x040000)
+#define IPN3KE_QOS_MAP_L2_MASK                 0x7
+#define IPN3KE_QOS_TYPE_MASK                   0x3
+#define IPN3KE_QOS_TYPE_L1_X                  (IPN3KE_QOS_OFFSET + 0x200000)
+#define IPN3KE_QOS_TYPE_L2_X                  (IPN3KE_QOS_OFFSET + 0x240000)
+#define IPN3KE_QOS_TYPE_L3_X                  (IPN3KE_QOS_OFFSET + 0x280000)
+#define IPN3KE_QOS_SCH_WT_MASK                 0xFF
+#define IPN3KE_QOS_SCH_WT_L1_X                (IPN3KE_QOS_OFFSET + 0x400000)
+#define IPN3KE_QOS_SCH_WT_L2_X                (IPN3KE_QOS_OFFSET + 0x440000)
+#define IPN3KE_QOS_SCH_WT_L3_X                (IPN3KE_QOS_OFFSET + 0x480000)
+#define IPN3KE_QOS_SHAP_WT_MASK                0x3FFF
+#define IPN3KE_QOS_SHAP_WT_L1_X               (IPN3KE_QOS_OFFSET + 0x600000)
+#define IPN3KE_QOS_SHAP_WT_L2_X               (IPN3KE_QOS_OFFSET + 0x640000)
+#define IPN3KE_QOS_SHAP_WT_L3_X               (IPN3KE_QOS_OFFSET + 0x680000)
+
+#define IPN3KE_CLF_BASE_DST_MAC_ADDR_HI       (IPN3KE_CLASSIFY_OFFSET + 0x0000)
+#define IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW      (IPN3KE_CLASSIFY_OFFSET + 0x0004)
+#define IPN3KE_CLF_QINQ_STAG                  (IPN3KE_CLASSIFY_OFFSET + 0x0008)
+#define IPN3KE_CLF_LKUP_ENABLE                (IPN3KE_CLASSIFY_OFFSET + 0x000C)
+#define IPN3KE_CLF_DFT_FLOW_ID                (IPN3KE_CLASSIFY_OFFSET + 0x0040)
+#define IPN3KE_CLF_RX_PARSE_CFG               (IPN3KE_CLASSIFY_OFFSET + 0x0080)
+#define IPN3KE_CLF_RX_STATS_CFG               (IPN3KE_CLASSIFY_OFFSET + 0x00C0)
+#define IPN3KE_CLF_RX_STATS_RPT               (IPN3KE_CLASSIFY_OFFSET + 0x00C4)
+#define IPN3KE_CLF_RX_TEST                    (IPN3KE_CLASSIFY_OFFSET + 0x0400)
+
+#define IPN3KE_CLF_EM_VERSION       (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000)
+#define IPN3KE_CLF_EM_NUM           (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0008)
+#define IPN3KE_CLF_EM_KEY_WDTH      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x000C)
+#define IPN3KE_CLF_EM_RES_WDTH      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0010)
+#define IPN3KE_CLF_EM_ALARMS        (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0014)
+#define IPN3KE_CLF_EM_DRC_RLAT      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0018)
+
+#define IPN3KE_CLF_MHL_VERSION      (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0000)
+#define IPN3KE_CLF_MHL_GEN_CTRL     (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0018)
+#define IPN3KE_CLF_MHL_MGMT_CTRL    (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0020)
+#define IPN3KE_CLF_MHL_MGMT_CTRL_BIT_BUSY      31
+#define IPN3KE_CLF_MHL_MGMT_CTRL_FLUSH         0x0
+#define IPN3KE_CLF_MHL_MGMT_CTRL_INSERT        0x1
+#define IPN3KE_CLF_MHL_MGMT_CTRL_DELETE        0x2
+#define IPN3KE_CLF_MHL_MGMT_CTRL_SEARCH        0x3
+#define IPN3KE_CLF_MHL_FATAL_0     (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0050)
+#define IPN3KE_CLF_MHL_MON_0       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0060)
+#define IPN3KE_CLF_MHL_TOTAL_ENTRIES   (IPN3KE_CLASSIFY_OFFSET + \
+					0x50000 + 0x0080)
+#define IPN3KE_CLF_MHL_ONEHIT_BUCKETS  (IPN3KE_CLASSIFY_OFFSET + \
+					0x50000 + 0x0084)
+#define IPN3KE_CLF_MHL_KEY_MASK         0xFFFFFFFF
+#define IPN3KE_CLF_MHL_KEY_0       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1000)
+#define IPN3KE_CLF_MHL_KEY_1       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1004)
+#define IPN3KE_CLF_MHL_KEY_2       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1008)
+#define IPN3KE_CLF_MHL_KEY_3       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x100C)
+#define IPN3KE_CLF_MHL_RES_MASK    0xFFFFFFFF
+#define IPN3KE_CLF_MHL_RES         (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x2000)
+
+#define IPN3KE_ASSERT(x) do {\
+	if (!(x)) \
+		rte_panic("IPN3KE: x"); \
+} while (0)
+
+extern struct ipn3ke_hw_cap hw_cap;
+
+int
+ipn3ke_rpst_dev_set_link_up(struct rte_eth_dev *dev);
+int
+ipn3ke_rpst_dev_set_link_down(struct rte_eth_dev *dev);
+int
+ipn3ke_rpst_link_update(struct rte_eth_dev *ethdev,
+	int wait_to_complete);
+void
+ipn3ke_rpst_promiscuous_enable(struct rte_eth_dev *ethdev);
+void
+ipn3ke_rpst_promiscuous_disable(struct rte_eth_dev *ethdev);
+void
+ipn3ke_rpst_allmulticast_enable(struct rte_eth_dev *ethdev);
+void
+ipn3ke_rpst_allmulticast_disable(struct rte_eth_dev *ethdev);
+int
+ipn3ke_rpst_mac_addr_set(struct rte_eth_dev *ethdev,
+		struct ether_addr *mac_addr);
+int
+ipn3ke_rpst_mtu_set(struct rte_eth_dev *ethdev, uint16_t mtu);
+
+int
+ipn3ke_rpst_init(struct rte_eth_dev *ethdev, void *init_params);
+int
+ipn3ke_rpst_uninit(struct rte_eth_dev *ethdev);
+
+
+/* IPN3KE_MASK is a macro used on 32 bit registers */
+#define IPN3KE_MASK(mask, shift) ((mask) << (shift))
+
+#define IPN3KE_MAC_CTRL_BASE_0    0x00000000
+#define IPN3KE_MAC_CTRL_BASE_1    0x00008000
+
+#define IPN3KE_MAC_STATS_MASK    0xFFFFFFFFF
+
+/* All the address are in 4Bytes*/
+#define IPN3KE_MAC_PRIMARY_MAC_ADDR0    0x0010
+#define IPN3KE_MAC_PRIMARY_MAC_ADDR1    0x0011
+
+#define IPN3KE_MAC_MAC_RESET_CONTROL    0x001F
+#define IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT    0
+#define IPN3KE_MAC_MAC_RESET_CONTROL_TX_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT)
+
+#define IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT    8
+#define IPN3KE_MAC_MAC_RESET_CONTROL_RX_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT)
+
+#define IPN3KE_MAC_TX_PACKET_CONTROL    0x0020
+#define IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT    0
+#define IPN3KE_MAC_TX_PACKET_CONTROL_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT)
+
+#define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE    0x002A
+#define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT    0
+#define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT)
+
+#define IPN3KE_MAC_TX_FRAME_MAXLENGTH    0x002C
+#define IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT    0
+#define IPN3KE_MAC_TX_FRAME_MAXLENGTH_MASK \
+	IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT)
+
+#define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL    0x0040
+#define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT    0
+#define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_MASK \
+	IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT)
+
+#define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA    0x0042
+#define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT    0
+#define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_MASK \
+	IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT)
+
+#define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA    0x0043
+#define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT    0
+#define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_MASK \
+	IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT)
+
+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE    0x0044
+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT    0
+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT)
+
+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT    1
+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_MASK \
+	IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT)
+
+#define IPN3KE_MAC_RX_TRANSFER_CONTROL    0x00A0
+#define IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT    0x0
+#define IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT)
+
+#define IPN3KE_MAC_RX_FRAME_CONTROL    0x00AC
+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT    0x0
+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT)
+
+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT    0x1
+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT)
+
+#define IPN3KE_MAC_FRAME_SIZE_MAX    9728
+#define IPN3KE_MAC_RX_FRAME_MAXLENGTH    0x00AE
+#define IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT    0
+#define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \
+	IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)
+
+#define IPN3KE_MAC_TX_STATS_CLR    0x0140
+#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT    0
+#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT)
+
+#define IPN3KE_MAC_RX_STATS_CLR    0x01C0
+#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT    0
+#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK \
+	IPN3KE_MASK(0x1, IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT)
+
+/*tx_stats_framesOK*/
+#define IPN3KE_MAC_TX_STATS_FRAMESOK_HI  0x0142
+#define IPN3KE_MAC_TX_STATS_FRAMESOK_LOW 0x0143
+
+/*rx_stats_framesOK*/
+#define IPN3KE_MAC_RX_STATS_FRAMESOK_HI  0x01C2
+#define IPN3KE_MAC_RX_STATS_FRAMESOK_LOW 0x01C3
+
+/*tx_stats_framesErr*/
+#define IPN3KE_MAC_TX_STATS_FRAMESERR_HI  0x0144
+#define IPN3KE_MAC_TX_STATS_FRAMESERR_LOW 0x0145
+
+/*rx_stats_framesErr*/
+#define IPN3KE_MAC_RX_STATS_FRAMESERR_HI  0x01C4
+#define IPN3KE_MAC_RX_STATS_FRAMESERR_LOW 0x01C5
+
+/*rx_stats_framesCRCErr*/
+#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_HI  0x01C6
+#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_LOW 0x01C7
+
+/*tx_stats_octetsOK 64b*/
+#define IPN3KE_MAC_TX_STATS_OCTETSOK_HI  0x0148
+#define IPN3KE_MAC_TX_STATS_OCTETSOK_LOW 0x0149
+
+/*rx_stats_octetsOK 64b*/
+#define IPN3KE_MAC_RX_STATS_OCTETSOK_HI  0x01C8
+#define IPN3KE_MAC_RX_STATS_OCTETSOK_LOW 0x01C9
+
+/*tx_stats_pauseMACCtrl_Frames*/
+#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_HI  0x014A
+#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x014B
+
+/*rx_stats_pauseMACCtrl_Frames*/
+#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_HI  0x01CA
+#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x01CB
+
+/*tx_stats_ifErrors*/
+#define IPN3KE_MAC_TX_STATS_IFERRORS_HI  0x014C
+#define IPN3KE_MAC_TX_STATS_IFERRORS_LOW 0x014D
+
+/*rx_stats_ifErrors*/
+#define IPN3KE_MAC_RX_STATS_IFERRORS_HI  0x01CC
+#define IPN3KE_MAC_RX_STATS_IFERRORS_LOW 0x01CD
+
+/*tx_stats_unicast_FramesOK*/
+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_HI  0x014E
+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_LOW 0x014F
+
+/*rx_stats_unicast_FramesOK*/
+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_HI  0x01CE
+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_LOW 0x01CF
+
+/*tx_stats_unicast_FramesErr*/
+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_HI  0x0150
+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_LOW 0x0151
+
+/*rx_stats_unicast_FramesErr*/
+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_HI  0x01D0
+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_LOW 0x01D1
+
+/*tx_stats_multicast_FramesOK*/
+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_HI  0x0152
+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_LOW 0x0153
+
+/*rx_stats_multicast_FramesOK*/
+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_HI  0x01D2
+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_LOW 0x01D3
+
+/*tx_stats_multicast_FramesErr*/
+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_HI  0x0154
+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_LOW 0x0155
+
+/*rx_stats_multicast_FramesErr*/
+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_HI  0x01D4
+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_LOW 0x01D5
+
+/*tx_stats_broadcast_FramesOK*/
+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_HI  0x0156
+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_LOW 0x0157
+
+/*rx_stats_broadcast_FramesOK*/
+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_HI  0x01D6
+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_LOW 0x01D7
+
+/*tx_stats_broadcast_FramesErr*/
+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_HI  0x0158
+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_LOW 0x0159
+
+/*rx_stats_broadcast_FramesErr*/
+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_HI  0x01D8
+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_LOW 0x01D9
+
+/*tx_stats_etherStatsOctets 64b*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_HI  0x015A
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_LOW 0x015B
+
+/*rx_stats_etherStatsOctets 64b*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_HI  0x01DA
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_LOW 0x01DB
+
+/*tx_stats_etherStatsPkts*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_HI  0x015C
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_LOW 0x015D
+
+/*rx_stats_etherStatsPkts*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_HI  0x01DC
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_LOW 0x01DD
+
+/*tx_stats_etherStatsUndersizePkts*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_HI  0x015E
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x015F
+
+/*rx_stats_etherStatsUndersizePkts*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_HI  0x01DE
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x01DF
+
+/*tx_stats_etherStatsOversizePkts*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_HI  0x0160
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x0161
+
+/*rx_stats_etherStatsOversizePkts*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_HI  0x01E0
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x01E1
+
+/*tx_stats_etherStatsPkts64Octets*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_HI  0x0162
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x0163
+
+/*rx_stats_etherStatsPkts64Octets*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_HI  0x01E2
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x01E3
+
+/*tx_stats_etherStatsPkts65to127Octets*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI  0x0164
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x0165
+
+/*rx_stats_etherStatsPkts65to127Octets*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI  0x01E4
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x01E5
+
+/*tx_stats_etherStatsPkts128to255Octets*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI  0x0166
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x0167
+
+/*rx_stats_etherStatsPkts128to255Octets*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI  0x01E6
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x01E7
+
+/*tx_stats_etherStatsPkts256to511Octet*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_HI  0x0168
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_LOW 0x0169
+
+/*rx_stats_etherStatsPkts256to511Octets*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_HI  0x01E8
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_LOW 0x01E9
+
+/*tx_stats_etherStatsPkts512to1023Octets*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI  0x016A
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x016B
+
+/*rx_stats_etherStatsPkts512to1023Octets*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI  0x01EA
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x01EB
+
+/*tx_stats_etherStatPkts1024to1518Octets*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI  0x016C
+#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x016D
+
+/*rx_stats_etherStatPkts1024to1518Octets*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI  0x01EC
+#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x01ED
+
+/*tx_stats_etherStatsPkts1519toXOctets*/
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI  0x016E
+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x016F
+
+/*rx_stats_etherStatsPkts1519toXOctets*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI  0x01EE
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x01EF
+
+/*rx_stats_etherStatsFragments*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_HI  0x01F0
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_LOW 0x01F1
+
+/*rx_stats_etherStatsJabbers*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_HI  0x01F2
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_LOW 0x01F3
+
+/*rx_stats_etherStatsCRCErr*/
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_HI  0x01F4
+#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_LOW 0x01F5
+
+/*tx_stats_unicastMACCtrlFrames*/
+#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_HI  0x0176
+#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_LOW 0x0177
+
+/*rx_stats_unicastMACCtrlFrames*/
+#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_HI  0x01F6
+#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_LOW 0x01F7
+
+/*tx_stats_multicastMACCtrlFrames*/
+#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_HI  0x0178
+#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x0179
+
+/*rx_stats_multicastMACCtrlFrames*/
+#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_HI  0x01F8
+#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x01F9
+
+/*tx_stats_broadcastMACCtrlFrames*/
+#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_HI  0x017A
+#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x017B
+
+/*rx_stats_broadcastMACCtrlFrames*/
+#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_HI  0x01FA
+#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x01FB
+
+/*tx_stats_PFCMACCtrlFrames*/
+#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_HI  0x017C
+#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_LOW 0x017D
+
+/*rx_stats_PFCMACCtrlFrames*/
+#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_HI  0x01FC
+#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_LOW 0x01FD
+
+
+#endif /* _IPN3KE_ETHDEV_H_ */
diff --git a/drivers/net/ipn3ke/ipn3ke_flow.c b/drivers/net/ipn3ke/ipn3ke_flow.c
new file mode 100644
index 0000000..ad5cd14
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_flow.c
@@ -0,0 +1,1407 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <sys/queue.h>
+#include <stdio.h>
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdarg.h>
+
+#include <rte_io.h>
+#include <rte_debug.h>
+#include <rte_ether.h>
+#include <rte_ethdev_driver.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+#include <rte_eth_ctrl.h>
+#include <rte_tailq.h>
+
+#include "ifpga_rawdev_api.h"
+#include "ipn3ke_tm.h"
+#include "ipn3ke_flow.h"
+#include "ipn3ke_logs.h"
+#include "ipn3ke_ethdev.h"
+
+#define DEBUG_IPN3KE_FLOW
+
+/** Static initializer for items. */
+#define FLOW_PATTERNS(...) \
+	((const enum rte_flow_item_type []) { \
+		__VA_ARGS__, RTE_FLOW_ITEM_TYPE_END, \
+	})
+
+enum IPN3KE_HASH_KEY_TYPE {
+	IPN3KE_HASH_KEY_VXLAN,
+	IPN3KE_HASH_KEY_MAC,
+	IPN3KE_HASH_KEY_QINQ,
+	IPN3KE_HASH_KEY_MPLS,
+	IPN3KE_HASH_KEY_IP_TCP,
+	IPN3KE_HASH_KEY_IP_UDP,
+	IPN3KE_HASH_KEY_IP_NVGRE,
+	IPN3KE_HASH_KEY_VXLAN_IP_UDP,
+};
+
+struct ipn3ke_flow_parse {
+	uint32_t mark:1; /**< Set if the flow is marked. */
+	uint32_t drop:1; /**< ACL drop. */
+	uint32_t key_type:IPN3KE_FLOW_KEY_ID_BITS;
+	uint32_t mark_id:IPN3KE_FLOW_RESULT_UID_BITS; /**< Mark identifier. */
+	uint8_t key_len; /**< Length in bit. */
+	uint8_t key[BITS_TO_BYTES(IPN3KE_FLOW_KEY_DATA_BITS)];
+		/**< key1, key2 */
+};
+
+typedef int (*pattern_filter_t)(const struct rte_flow_item patterns[],
+					struct rte_flow_error *error,
+					struct ipn3ke_flow_parse *parser);
+
+
+struct ipn3ke_flow_pattern {
+	const enum rte_flow_item_type *const items;
+
+	pattern_filter_t filter;
+};
+
+/*
+ * @ RTL definition:
+ * typedef struct packed {
+ * logic [47:0]    vxlan_inner_mac;
+ * logic [23:0]    vxlan_vni;
+ * } Hash_Key_Vxlan_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_VXLAN
+ * RTE_FLOW_ITEM_TYPE_ETH
+ */
+static int
+ipn3ke_pattern_vxlan(const struct rte_flow_item patterns[],
+		struct rte_flow_error *error,
+		struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_vxlan *vxlan = NULL;
+	const struct rte_flow_item_eth *eth = NULL;
+	const struct rte_flow_item *item;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (/*!item->spec || item->mask || */item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_ETH:
+			eth = item->spec;
+
+			rte_memcpy(&parser->key[0],
+					eth->src.addr_bytes,
+					ETHER_ADDR_LEN);
+			break;
+
+		case RTE_FLOW_ITEM_TYPE_VXLAN:
+			vxlan = item->spec;
+
+			rte_memcpy(&parser->key[6], vxlan->vni, 3);
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (vxlan != NULL && eth != NULL) {
+		parser->key_len = 48 + 24;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+/*
+ * @ RTL definition:
+ * typedef struct packed {
+ * logic [47:0]    eth_smac;
+ * } Hash_Key_Mac_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_ETH
+ */
+static int
+ipn3ke_pattern_mac(const struct rte_flow_item patterns[],
+		 struct rte_flow_error *error,
+		 struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_eth *eth = NULL;
+	const struct rte_flow_item *item;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (!item->spec || item->mask || item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_ETH:
+			eth = item->spec;
+
+			rte_memcpy(parser->key,
+					eth->src.addr_bytes,
+					ETHER_ADDR_LEN);
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (eth != NULL) {
+		parser->key_len = 48;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+/*
+ * @ RTL definition:
+ * typedef struct packed {
+ * logic [11:0]    outer_vlan_id;
+ * logic [11:0]    inner_vlan_id;
+ * } Hash_Key_QinQ_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_VLAN
+ * RTE_FLOW_ITEM_TYPE_VLAN
+ */
+static int
+ipn3ke_pattern_qinq(const struct rte_flow_item patterns[],
+		struct rte_flow_error *error,
+		struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_vlan *outer_vlan = NULL;
+	const struct rte_flow_item_vlan *inner_vlan = NULL;
+	const struct rte_flow_item *item;
+	uint16_t tci;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (!item->spec || item->mask || item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_VLAN:
+			if (!outer_vlan) {
+				outer_vlan = item->spec;
+
+				tci = rte_be_to_cpu_16(outer_vlan->tci);
+				parser->key[0]  = (tci & 0xff0) >> 4;
+				parser->key[1] |= (tci & 0x00f) << 4;
+			} else {
+				inner_vlan = item->spec;
+
+				tci = rte_be_to_cpu_16(inner_vlan->tci);
+				parser->key[1] |= (tci & 0xf00) >> 8;
+				parser->key[2]  = (tci & 0x0ff);
+			}
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (outer_vlan != NULL && inner_vlan != NULL) {
+		parser->key_len = 12 + 12;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+/*
+ * @ RTL definition:
+ * typedef struct packed {
+ * logic [19:0]    mpls_label1;
+ * logic [19:0]    mpls_label2;
+ * } Hash_Key_Mpls_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_MPLS
+ * RTE_FLOW_ITEM_TYPE_MPLS
+ */
+static int
+ipn3ke_pattern_mpls(const struct rte_flow_item patterns[],
+		struct rte_flow_error *error,
+		struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_mpls *mpls1 = NULL;
+	const struct rte_flow_item_mpls *mpls2 = NULL;
+	const struct rte_flow_item *item;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (!item->spec || item->mask || item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_MPLS:
+			if (!mpls1) {
+				mpls1 = item->spec;
+
+				parser->key[0] = mpls1->label_tc_s[0];
+				parser->key[1] = mpls1->label_tc_s[1];
+				parser->key[2] = mpls1->label_tc_s[2] & 0xf0;
+			} else {
+				mpls2 = item->spec;
+
+				parser->key[2] |=
+					((mpls2->label_tc_s[0] & 0xf0) >> 4);
+				parser->key[3] =
+					((mpls2->label_tc_s[0] & 0xf) << 4) |
+					((mpls2->label_tc_s[1] & 0xf0) >> 4);
+				parser->key[4] =
+					((mpls2->label_tc_s[1] & 0xf) << 4) |
+					((mpls2->label_tc_s[2] & 0xf0) >> 4);
+			}
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (mpls1 != NULL && mpls2 != NULL) {
+		parser->key_len = 20 + 20;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+/*
+ * @ RTL definition:
+ * typedef struct packed {
+ * logic [31:0]    ip_sa;
+ * logic [15:0]    tcp_sport;
+ * } Hash_Key_Ip_Tcp_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_IPV4
+ * RTE_FLOW_ITEM_TYPE_TCP
+ */
+static int
+ipn3ke_pattern_ip_tcp(const struct rte_flow_item patterns[],
+		struct rte_flow_error *error,
+		struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_ipv4 *ipv4 = NULL;
+	const struct rte_flow_item_tcp *tcp = NULL;
+	const struct rte_flow_item *item;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (!item->spec || item->mask || item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_IPV4:
+			ipv4 = item->spec;
+
+			rte_memcpy(&parser->key[0], &ipv4->hdr.src_addr, 4);
+			break;
+
+		case RTE_FLOW_ITEM_TYPE_TCP:
+			tcp = item->spec;
+
+			rte_memcpy(&parser->key[4], &tcp->hdr.src_port, 2);
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (ipv4 != NULL && tcp != NULL) {
+		parser->key_len = 32 + 16;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+/*
+ * @ RTL definition:
+ * typedef struct packed {
+ * logic [31:0]    ip_sa;
+ * logic [15:0]    udp_sport;
+ * } Hash_Key_Ip_Udp_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_IPV4
+ * RTE_FLOW_ITEM_TYPE_UDP
+ */
+static int
+ipn3ke_pattern_ip_udp(const struct rte_flow_item patterns[],
+		struct rte_flow_error *error,
+		struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_ipv4 *ipv4 = NULL;
+	const struct rte_flow_item_udp *udp = NULL;
+	const struct rte_flow_item *item;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (!item->spec || item->mask || item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_IPV4:
+			ipv4 = item->spec;
+
+			rte_memcpy(&parser->key[0], &ipv4->hdr.src_addr, 4);
+			break;
+
+		case RTE_FLOW_ITEM_TYPE_UDP:
+			udp = item->spec;
+
+			rte_memcpy(&parser->key[4], &udp->hdr.src_port, 2);
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (ipv4 != NULL && udp != NULL) {
+		parser->key_len = 32 + 16;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+/*
+ * @ RTL definition:
+ * typedef struct packed {
+ * logic [31:0]    ip_sa;
+ * logic [15:0]    udp_sport;
+ * logic [23:0]    vsid;
+ * } Hash_Key_Ip_Nvgre_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_IPV4
+ * RTE_FLOW_ITEM_TYPE_UDP
+ * RTE_FLOW_ITEM_TYPE_NVGRE
+ */
+static int
+ipn3ke_pattern_ip_nvgre(const struct rte_flow_item patterns[],
+		struct rte_flow_error *error,
+		struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_nvgre *nvgre = NULL;
+	const struct rte_flow_item_ipv4 *ipv4 = NULL;
+	const struct rte_flow_item_udp *udp = NULL;
+	const struct rte_flow_item *item;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (!item->spec || item->mask || item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_IPV4:
+			ipv4 = item->spec;
+
+			rte_memcpy(&parser->key[0], &ipv4->hdr.src_addr, 4);
+			break;
+
+		case RTE_FLOW_ITEM_TYPE_UDP:
+			udp = item->spec;
+
+			rte_memcpy(&parser->key[4], &udp->hdr.src_port, 2);
+			break;
+
+		case RTE_FLOW_ITEM_TYPE_NVGRE:
+			nvgre = item->spec;
+
+			rte_memcpy(&parser->key[6], nvgre->tni, 3);
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (ipv4 != NULL && udp != NULL && nvgre != NULL) {
+		parser->key_len = 32 + 16 + 24;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+/*
+ * @ RTL definition:
+ * typedef struct packed{
+ * logic [23:0]    vxlan_vni;
+ * logic [31:0]    ip_sa;
+ * logic [15:0]    udp_sport;
+ * } Hash_Key_Vxlan_Ip_Udp_t;
+ *
+ * @ flow items:
+ * RTE_FLOW_ITEM_TYPE_VXLAN
+ * RTE_FLOW_ITEM_TYPE_IPV4
+ * RTE_FLOW_ITEM_TYPE_UDP
+ */
+static int
+ipn3ke_pattern_vxlan_ip_udp(const struct rte_flow_item patterns[],
+				struct rte_flow_error *error,
+				struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_item_vxlan *vxlan = NULL;
+	const struct rte_flow_item_ipv4 *ipv4 = NULL;
+	const struct rte_flow_item_udp *udp = NULL;
+	const struct rte_flow_item *item;
+
+	for (item = patterns; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		if (!item->spec || item->mask || item->last) {
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Only support item with 'spec'");
+			return -rte_errno;
+		}
+
+		switch (item->type) {
+		case RTE_FLOW_ITEM_TYPE_VXLAN:
+			vxlan = item->spec;
+
+			rte_memcpy(&parser->key[0], vxlan->vni, 3);
+			break;
+
+		case RTE_FLOW_ITEM_TYPE_IPV4:
+			ipv4 = item->spec;
+
+			rte_memcpy(&parser->key[3], &ipv4->hdr.src_addr, 4);
+			break;
+
+		case RTE_FLOW_ITEM_TYPE_UDP:
+			udp = item->spec;
+
+			rte_memcpy(&parser->key[7], &udp->hdr.src_port, 2);
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					EINVAL,
+					RTE_FLOW_ERROR_TYPE_ITEM,
+					item,
+					"Not support item type");
+			return -rte_errno;
+		}
+	}
+
+	if (vxlan != NULL && ipv4 != NULL && udp != NULL) {
+		parser->key_len = 24 + 32 + 16;
+		return 0;
+	}
+
+	rte_flow_error_set(error,
+			EINVAL,
+			RTE_FLOW_ERROR_TYPE_ITEM,
+			patterns,
+			"Missed some patterns");
+	return -rte_errno;
+}
+
+static const struct ipn3ke_flow_pattern ipn3ke_supported_patterns[] = {
+	[IPN3KE_HASH_KEY_VXLAN] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_VXLAN,
+					RTE_FLOW_ITEM_TYPE_ETH),
+		.filter = ipn3ke_pattern_vxlan,
+	},
+
+	[IPN3KE_HASH_KEY_MAC] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_ETH),
+		.filter = ipn3ke_pattern_mac,
+	},
+
+	[IPN3KE_HASH_KEY_QINQ] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_VLAN,
+					RTE_FLOW_ITEM_TYPE_VLAN),
+		.filter = ipn3ke_pattern_qinq,
+	},
+
+	[IPN3KE_HASH_KEY_MPLS] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_MPLS,
+					RTE_FLOW_ITEM_TYPE_MPLS),
+		.filter = ipn3ke_pattern_mpls,
+	},
+
+	[IPN3KE_HASH_KEY_IP_TCP] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_IPV4,
+					RTE_FLOW_ITEM_TYPE_TCP),
+		.filter = ipn3ke_pattern_ip_tcp,
+	},
+
+	[IPN3KE_HASH_KEY_IP_UDP] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_IPV4,
+					RTE_FLOW_ITEM_TYPE_UDP),
+		.filter = ipn3ke_pattern_ip_udp,
+	},
+
+	[IPN3KE_HASH_KEY_IP_NVGRE] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_IPV4,
+					RTE_FLOW_ITEM_TYPE_UDP,
+					RTE_FLOW_ITEM_TYPE_NVGRE),
+		.filter = ipn3ke_pattern_ip_nvgre,
+	},
+
+	[IPN3KE_HASH_KEY_VXLAN_IP_UDP] = {
+		.items = FLOW_PATTERNS(RTE_FLOW_ITEM_TYPE_VXLAN,
+					RTE_FLOW_ITEM_TYPE_IPV4,
+					RTE_FLOW_ITEM_TYPE_UDP),
+		.filter = ipn3ke_pattern_vxlan_ip_udp,
+	},
+};
+
+static int
+ipn3ke_flow_convert_attributes(const struct rte_flow_attr *attr,
+				struct rte_flow_error *error)
+{
+	if (!attr) {
+		rte_flow_error_set(error,
+				EINVAL,
+				RTE_FLOW_ERROR_TYPE_ATTR,
+				NULL,
+				"NULL attribute.");
+		return -rte_errno;
+	}
+
+	if (attr->group) {
+		rte_flow_error_set(error,
+				ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
+				NULL,
+				"groups are not supported");
+		return -rte_errno;
+	}
+
+	if (attr->egress) {
+		rte_flow_error_set(error,
+				ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
+				NULL,
+				"egress is not supported");
+		return -rte_errno;
+	}
+
+	if (attr->transfer) {
+		rte_flow_error_set(error,
+				ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
+				NULL,
+				"transfer is not supported");
+		return -rte_errno;
+	}
+
+	if (!attr->ingress) {
+		rte_flow_error_set(error,
+				ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
+				NULL,
+				"only ingress is supported");
+		return -rte_errno;
+	}
+
+	return 0;
+}
+
+static int
+ipn3ke_flow_convert_actions(const struct rte_flow_action actions[],
+				struct rte_flow_error *error,
+				struct ipn3ke_flow_parse *parser)
+{
+	const struct rte_flow_action_mark *mark = NULL;
+
+	if (!actions) {
+		rte_flow_error_set(error,
+				EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION_NUM,
+				NULL,
+				"NULL action.");
+		return -rte_errno;
+	}
+
+	for (; actions->type != RTE_FLOW_ACTION_TYPE_END; ++actions) {
+		switch (actions->type) {
+		case RTE_FLOW_ACTION_TYPE_VOID:
+			break;
+
+		case RTE_FLOW_ACTION_TYPE_MARK:
+			if (mark) {
+				rte_flow_error_set(error,
+						ENOTSUP,
+						RTE_FLOW_ERROR_TYPE_ACTION,
+						actions,
+						"duplicated mark");
+				return -rte_errno;
+			}
+
+			mark = actions->conf;
+			if (!mark) {
+				rte_flow_error_set(error,
+						EINVAL,
+						RTE_FLOW_ERROR_TYPE_ACTION,
+						actions,
+						"mark must be defined");
+				return -rte_errno;
+			} else if (mark->id > IPN3KE_FLOW_RESULT_UID_MAX) {
+				rte_flow_error_set(error,
+						ENOTSUP,
+						RTE_FLOW_ERROR_TYPE_ACTION,
+						actions,
+						"mark id is out of range");
+				return -rte_errno;
+			}
+
+			parser->mark = 1;
+			parser->mark_id = mark->id;
+			break;
+
+		case RTE_FLOW_ACTION_TYPE_DROP:
+			parser->drop = 1;
+			break;
+
+		default:
+			rte_flow_error_set(error,
+					ENOTSUP,
+					RTE_FLOW_ERROR_TYPE_ACTION,
+					actions,
+					"invalid action");
+			return -rte_errno;
+		}
+	}
+
+	if (!parser->drop && !parser->mark) {
+		rte_flow_error_set(error,
+				EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION,
+				actions,
+				"no valid actions");
+		return -rte_errno;
+	}
+
+	return 0;
+}
+
+static bool
+ipn3ke_match_pattern(const enum rte_flow_item_type *patterns,
+				const struct rte_flow_item *input)
+{
+	const struct rte_flow_item *item = input;
+
+	while ((*patterns == item->type) &&
+		(*patterns != RTE_FLOW_ITEM_TYPE_END)) {
+		patterns++;
+		item++;
+	}
+
+	return (*patterns == RTE_FLOW_ITEM_TYPE_END &&
+		item->type == RTE_FLOW_ITEM_TYPE_END);
+}
+
+static pattern_filter_t
+ipn3ke_find_filter_func(const struct rte_flow_item *input,
+				uint32_t *idx)
+{
+	pattern_filter_t filter = NULL;
+	uint32_t i;
+
+	for (i = 0; i < RTE_DIM(ipn3ke_supported_patterns); i++) {
+		if (ipn3ke_match_pattern(ipn3ke_supported_patterns[i].items,
+					input)) {
+			filter = ipn3ke_supported_patterns[i].filter;
+			*idx = i;
+			break;
+		}
+	}
+
+	return filter;
+}
+
+static int
+ipn3ke_flow_convert_items(const struct rte_flow_item items[],
+			struct rte_flow_error *error,
+			struct ipn3ke_flow_parse *parser)
+{
+	pattern_filter_t filter = NULL;
+	uint32_t idx;
+
+	if (!items) {
+		rte_flow_error_set(error,
+				EINVAL,
+				RTE_FLOW_ERROR_TYPE_ITEM_NUM,
+				NULL,
+				"NULL pattern.");
+		return -rte_errno;
+	}
+
+	filter = ipn3ke_find_filter_func(items, &idx);
+
+	if (!filter) {
+		rte_flow_error_set(error,
+				EINVAL,
+				RTE_FLOW_ERROR_TYPE_ITEM,
+				items,
+				"Unsupported pattern");
+		return -rte_errno;
+	}
+
+	parser->key_type = idx;
+
+	return filter(items, error, parser);
+}
+
+/* Put the least @nbits of @data into @offset of @dst bits stream, and
+ * the @offset starts from MSB to LSB in each byte.
+ *
+ * MSB    LSB
+ *  +------+------+------+------+
+ *  |      |      |      |      |
+ *  +------+------+------+------+
+ *       ^                 ^
+ *       |<- data: nbits ->|
+ *       |
+ *     offset
+ */
+static void
+copy_data_bits(uint8_t *dst, uint64_t data,
+		uint32_t offset, uint8_t nbits)
+{
+	uint8_t set, *p = &dst[offset / BITS_PER_BYTE];
+	uint8_t bits_to_set = BITS_PER_BYTE - (offset % BITS_PER_BYTE);
+	uint8_t mask_to_set = 0xff >> (offset % BITS_PER_BYTE);
+	uint32_t size = offset + nbits;
+
+	if (nbits > (sizeof(data) * BITS_PER_BYTE)) {
+		IPN3KE_AFU_PMD_ERR("nbits is out of range");
+		return;
+	}
+
+	while (nbits - bits_to_set >= 0) {
+		set = data >> (nbits - bits_to_set);
+
+		*p &= ~mask_to_set;
+		*p |= (set & mask_to_set);
+
+		nbits -= bits_to_set;
+		bits_to_set = BITS_PER_BYTE;
+		mask_to_set = 0xff;
+		p++;
+	}
+
+	if (nbits) {
+		uint8_t shift = BITS_PER_BYTE - (size % BITS_PER_BYTE);
+
+		set = data << shift;
+		mask_to_set = 0xff << shift;
+
+		*p &= ~mask_to_set;
+		*p |= (set & mask_to_set);
+	}
+}
+
+static void
+ipn3ke_flow_key_generation(struct ipn3ke_flow_parse *parser,
+				struct rte_flow *flow)
+{
+	uint32_t i, shift_bytes, len_in_bytes, offset;
+	uint64_t key;
+	uint8_t *dst;
+
+	dst = flow->rule.key;
+
+	copy_data_bits(dst,
+			parser->key_type,
+			IPN3KE_FLOW_KEY_ID_OFFSET,
+			IPN3KE_FLOW_KEY_ID_BITS);
+
+	/* The MSb of key is filled to 0 when it is less than
+	 * IPN3KE_FLOW_KEY_DATA_BITS bit. And the parsed key data is
+	 * save as MSB byte first in the array, it needs to move
+	 * the bits before formatting them.
+	 */
+	key = 0;
+	shift_bytes = 0;
+	len_in_bytes = BITS_TO_BYTES(parser->key_len);
+	offset = (IPN3KE_FLOW_KEY_DATA_OFFSET +
+		IPN3KE_FLOW_KEY_DATA_BITS -
+		parser->key_len);
+
+	for (i = 0; i < len_in_bytes; i++) {
+		key = (key << 8) | parser->key[i];
+
+		if (++shift_bytes == sizeof(key)) {
+			shift_bytes = 0;
+
+			copy_data_bits(dst, key, offset,
+					sizeof(key) * BITS_PER_BYTE);
+			offset += sizeof(key) * BITS_PER_BYTE;
+			key = 0;
+		}
+	}
+
+	if (shift_bytes != 0) {
+		uint32_t rem_bits;
+
+		rem_bits = parser->key_len % (sizeof(key) * BITS_PER_BYTE);
+		key >>= (shift_bytes * 8 - rem_bits);
+		copy_data_bits(dst, key, offset, rem_bits);
+	}
+}
+
+static void
+ipn3ke_flow_result_generation(struct ipn3ke_flow_parse *parser,
+				struct rte_flow *flow)
+{
+	uint8_t *dst;
+
+	if (parser->drop)
+		return;
+
+	dst = flow->rule.result;
+
+	copy_data_bits(dst,
+			1,
+			IPN3KE_FLOW_RESULT_ACL_OFFSET,
+			IPN3KE_FLOW_RESULT_ACL_BITS);
+
+	copy_data_bits(dst,
+			parser->mark_id,
+			IPN3KE_FLOW_RESULT_UID_OFFSET,
+			IPN3KE_FLOW_RESULT_UID_BITS);
+}
+
+#define	__SWAP16(_x)				\
+	((((_x) & 0xff) << 8) |			\
+	(((_x) >> 8) & 0xff))
+
+#define	__SWAP32(_x)				\
+	((__SWAP16((_x) & 0xffff) << 16) |	\
+	__SWAP16(((_x) >> 16) & 0xffff))
+
+#define MHL_COMMAND_TIME_COUNT        0xFFFF
+#define MHL_COMMAND_TIME_INTERVAL_US  10
+
+static int
+ipn3ke_flow_hw_update(struct ipn3ke_hw *hw,
+			struct rte_flow *flow, uint32_t is_add)
+{
+	uint32_t *pdata = NULL;
+	uint32_t data;
+	uint32_t time_out = MHL_COMMAND_TIME_COUNT;
+
+#ifdef DEBUG_IPN3KE_FLOW
+	uint32_t i;
+
+	printf("IPN3KE flow dump\n");
+
+	pdata = (uint32_t *)flow->rule.key;
+	printf(" - key   :");
+
+	for (i = 0; i < RTE_DIM(flow->rule.key); i++)
+		printf(" %02x", flow->rule.key[i]);
+
+	for (i = 0; i < 4; i++)
+		printf(" %02x", __SWAP32(pdata[3 - i]));
+	printf("\n");
+
+	pdata = (uint32_t *)flow->rule.result;
+	printf(" - result:");
+
+	for (i = 0; i < RTE_DIM(flow->rule.result); i++)
+		printf(" %02x", flow->rule.result[i]);
+
+	for (i = 0; i < 1; i++)
+		printf(" %02x", pdata[i]);
+	printf("\n");
+#endif
+
+	pdata = (uint32_t *)flow->rule.key;
+
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_KEY_0,
+			0,
+			__SWAP32(pdata[3]),
+			IPN3KE_CLF_MHL_KEY_MASK);
+
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_KEY_1,
+			0,
+			__SWAP32(pdata[2]),
+			IPN3KE_CLF_MHL_KEY_MASK);
+
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_KEY_2,
+			0,
+			__SWAP32(pdata[1]),
+			IPN3KE_CLF_MHL_KEY_MASK);
+
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_KEY_3,
+			0,
+			__SWAP32(pdata[0]),
+			IPN3KE_CLF_MHL_KEY_MASK);
+
+	pdata = (uint32_t *)flow->rule.result;
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_RES,
+			0,
+			__SWAP32(pdata[0]),
+			IPN3KE_CLF_MHL_RES_MASK);
+
+	/* insert/delete the key and result */
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_MHL_MGMT_CTRL,
+				0,
+				0x80000000);
+	time_out = MHL_COMMAND_TIME_COUNT;
+	while (IPN3KE_BIT_ISSET(data, IPN3KE_CLF_MHL_MGMT_CTRL_BIT_BUSY) &&
+		(time_out > 0)) {
+		data = IPN3KE_MASK_READ_REG(hw,
+					IPN3KE_CLF_MHL_MGMT_CTRL,
+					0,
+					0x80000000);
+		time_out--;
+		rte_delay_us(MHL_COMMAND_TIME_INTERVAL_US);
+	}
+	if (!time_out)
+		return -1;
+	if (is_add)
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_CLF_MHL_MGMT_CTRL,
+				0,
+				IPN3KE_CLF_MHL_MGMT_CTRL_INSERT,
+				0x3);
+	else
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_CLF_MHL_MGMT_CTRL,
+				0,
+				IPN3KE_CLF_MHL_MGMT_CTRL_DELETE,
+				0x3);
+
+	return 0;
+}
+
+static int
+ipn3ke_flow_hw_flush(struct ipn3ke_hw *hw)
+{
+	uint32_t data;
+	uint32_t time_out = MHL_COMMAND_TIME_COUNT;
+
+	/* flush the MHL lookup table */
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_MHL_MGMT_CTRL,
+				0,
+				0x80000000);
+	time_out = MHL_COMMAND_TIME_COUNT;
+	while (IPN3KE_BIT_ISSET(data, IPN3KE_CLF_MHL_MGMT_CTRL_BIT_BUSY) &&
+		(time_out > 0)) {
+		data = IPN3KE_MASK_READ_REG(hw,
+					IPN3KE_CLF_MHL_MGMT_CTRL,
+					0,
+					0x80000000);
+		time_out--;
+		rte_delay_us(MHL_COMMAND_TIME_INTERVAL_US);
+	}
+	if (!time_out)
+		return -1;
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_MGMT_CTRL,
+			0,
+			IPN3KE_CLF_MHL_MGMT_CTRL_FLUSH,
+			0x3);
+
+	return 0;
+}
+
+static void
+ipn3ke_flow_convert_finalise(struct ipn3ke_hw *hw,
+				struct ipn3ke_flow_parse *parser,
+				struct rte_flow *flow)
+{
+	ipn3ke_flow_key_generation(parser, flow);
+	ipn3ke_flow_result_generation(parser, flow);
+	ipn3ke_flow_hw_update(hw, flow, 1);
+}
+
+static int
+ipn3ke_flow_convert(const struct rte_flow_attr *attr,
+		const struct rte_flow_item items[],
+		const struct rte_flow_action actions[],
+		struct rte_flow_error *error,
+		struct ipn3ke_flow_parse *parser)
+{
+	int ret;
+
+	ret = ipn3ke_flow_convert_attributes(attr, error);
+	if (ret)
+		return ret;
+
+	ret = ipn3ke_flow_convert_actions(actions, error, parser);
+	if (ret)
+		return ret;
+
+	ret = ipn3ke_flow_convert_items(items, error, parser);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int
+ipn3ke_flow_validate(__rte_unused struct rte_eth_dev *dev,
+		const struct rte_flow_attr *attr,
+		const struct rte_flow_item pattern[],
+		const struct rte_flow_action actions[],
+		struct rte_flow_error *error)
+{
+	struct ipn3ke_flow_parse parser = { };
+	return ipn3ke_flow_convert(attr, pattern, actions, error, &parser);
+}
+
+static struct rte_flow *
+ipn3ke_flow_create(struct rte_eth_dev *dev,
+		const struct rte_flow_attr *attr,
+		const struct rte_flow_item pattern[],
+		const struct rte_flow_action actions[],
+		struct rte_flow_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_flow_parse parser = { };
+	struct rte_flow *flow;
+	int ret;
+
+	if (hw->flow_num_entries == hw->flow_max_entries) {
+		rte_flow_error_set(error,
+				ENOBUFS,
+				RTE_FLOW_ERROR_TYPE_HANDLE,
+				NULL,
+				"The flow table is full.");
+		return NULL;
+	}
+
+	ret = ipn3ke_flow_convert(attr, pattern, actions, error, &parser);
+	if (ret < 0) {
+		rte_flow_error_set(error,
+				-ret,
+				RTE_FLOW_ERROR_TYPE_HANDLE,
+				NULL,
+				"Failed to create flow.");
+		return NULL;
+	}
+
+	flow = rte_zmalloc("ipn3ke_flow", sizeof(struct rte_flow), 0);
+	if (!flow) {
+		rte_flow_error_set(error,
+				ENOMEM,
+				RTE_FLOW_ERROR_TYPE_HANDLE,
+				NULL,
+				"Failed to allocate memory");
+		return flow;
+	}
+
+	ipn3ke_flow_convert_finalise(hw, &parser, flow);
+
+	TAILQ_INSERT_TAIL(&hw->flow_list, flow, next);
+
+	return flow;
+}
+
+static int
+ipn3ke_flow_destroy(struct rte_eth_dev *dev,
+		struct rte_flow *flow,
+		struct rte_flow_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	int ret = 0;
+
+	ret = ipn3ke_flow_hw_update(hw, flow, 0);
+	if (!ret) {
+		TAILQ_REMOVE(&hw->flow_list, flow, next);
+		rte_free(flow);
+	} else {
+		rte_flow_error_set(error,
+				-ret,
+				RTE_FLOW_ERROR_TYPE_HANDLE,
+				NULL,
+				"Failed to destroy flow.");
+	}
+
+	return ret;
+}
+
+static int
+ipn3ke_flow_flush(struct rte_eth_dev *dev,
+		struct rte_flow_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct rte_flow *flow, *temp;
+
+	TAILQ_FOREACH_SAFE(flow, &hw->flow_list, next, temp) {
+		TAILQ_REMOVE(&hw->flow_list, flow, next);
+		rte_free(flow);
+	}
+
+	return ipn3ke_flow_hw_flush(hw);
+}
+
+int ipn3ke_flow_init(void *dev)
+{
+	struct ipn3ke_hw *hw = (struct ipn3ke_hw *)dev;
+	uint32_t data;
+
+	/* disable rx classifier bypass */
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_RX_TEST,
+			0, 0, 0x1);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_RX_TEST,
+				0,
+				0x1);
+	printf("IPN3KE_CLF_RX_TEST: %x\n", data);
+#endif
+
+	/* configure base mac address */
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_BASE_DST_MAC_ADDR_HI,
+			0,
+			0x2457,
+			0xFFFF);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_BASE_DST_MAC_ADDR_HI,
+				0,
+				0xFFFF);
+	printf("IPN3KE_CLF_BASE_DST_MAC_ADDR_HI: %x\n", data);
+#endif
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW,
+			0,
+			0x9bdf1000,
+			0xFFFFFFFF);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW,
+				0,
+				0xFFFFFFFF);
+	printf("IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW: %x\n", data);
+#endif
+
+	/* configure hash lookup rules enable */
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_LKUP_ENABLE,
+			0,
+			0xFD,
+			0xFF);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_LKUP_ENABLE,
+				0,
+				0xFF);
+	printf("IPN3KE_CLF_LKUP_ENABLE: %x\n", data);
+#endif
+
+	/* configure rx parse config, settings associatied with VxLAN */
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_RX_PARSE_CFG,
+			0,
+			0x212b5,
+			0x3FFFF);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_RX_PARSE_CFG,
+				0,
+				0x3FFFF);
+	printf("IPN3KE_CLF_RX_PARSE_CFG: %x\n", data);
+#endif
+
+	/* configure QinQ S-Tag */
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_QINQ_STAG,
+			0,
+			0x88a8,
+			0xFFFF);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_QINQ_STAG,
+				0,
+				0xFFFF);
+	printf("IPN3KE_CLF_QINQ_STAG: %x\n", data);
+#endif
+
+	/* configure gen ctrl */
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_GEN_CTRL,
+			0,
+			0x3,
+			0x3);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_MHL_GEN_CTRL,
+				0,
+				0x1F);
+	printf("IPN3KE_CLF_MHL_GEN_CTRL: %x\n", data);
+#endif
+
+	/* clear monitoring register */
+	IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_CLF_MHL_MON_0,
+			0,
+			0xFFFFFFFF,
+			0xFFFFFFFF);
+#ifdef DEBUG_IPN3KE_FLOW
+	data = 0;
+	data = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CLF_MHL_MON_0,
+				0,
+				0xFFFFFFFF);
+	printf("IPN3KE_CLF_MHL_MON_0: %x\n", data);
+#endif
+
+	ipn3ke_flow_hw_flush(hw);
+
+	TAILQ_INIT(&hw->flow_list);
+	hw->flow_max_entries = IPN3KE_MASK_READ_REG(hw,
+						IPN3KE_CLF_EM_NUM,
+						0,
+						0xFFFFFFFF);
+	hw->flow_num_entries = 0;
+
+	return 0;
+}
+
+const struct rte_flow_ops ipn3ke_flow_ops = {
+	.validate = ipn3ke_flow_validate,
+	.create = ipn3ke_flow_create,
+	.destroy = ipn3ke_flow_destroy,
+	.flush = ipn3ke_flow_flush,
+};
+
diff --git a/drivers/net/ipn3ke/ipn3ke_flow.h b/drivers/net/ipn3ke/ipn3ke_flow.h
new file mode 100644
index 0000000..d5356a8
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_flow.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _IPN3KE_FLOW_H_
+#define _IPN3KE_FLOW_H_
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <limits.h>
+#include <net/if.h>
+#include <netinet/in.h>
+#include <sys/queue.h>
+
+#include <rte_mbuf.h>
+#include <rte_flow_driver.h>
+#include <rte_ethdev_driver.h>
+#include <rte_ethdev_vdev.h>
+#include <rte_malloc.h>
+#include <rte_memcpy.h>
+#include <rte_bus_vdev.h>
+#include <rte_kvargs.h>
+#include <rte_spinlock.h>
+
+/**
+ * Expand the length to DWORD alignment with 'Unused' field.
+ *
+ * FLOW KEY:
+ *  | Unused |Ruler id (id)  | Key1 Key2 … (data) |
+ *  |--------+---------------+--------------------|
+ *  | 17bits |    3 bits     |   Total 108 bits   |
+ * MSB                 --->                      LSB
+ *
+ * Note: And the MSb of key data is filled to 0 when it is less
+ *       than 108 bit.
+ */
+#define IPN3KE_FLOW_KEY_UNUSED_BITS  17
+#define IPN3KE_FLOW_KEY_ID_BITS      3
+#define IPN3KE_FLOW_KEY_DATA_BITS    108
+
+#define IPN3KE_FLOW_KEY_TOTAL_BITS \
+		(IPN3KE_FLOW_KEY_UNUSED_BITS + \
+		IPN3KE_FLOW_KEY_ID_BITS + \
+		IPN3KE_FLOW_KEY_DATA_BITS)
+
+#define IPN3KE_FLOW_KEY_ID_OFFSET \
+		(IPN3KE_FLOW_KEY_UNUSED_BITS)
+
+#define IPN3KE_FLOW_KEY_DATA_OFFSET \
+		(IPN3KE_FLOW_KEY_ID_OFFSET + IPN3KE_FLOW_KEY_ID_BITS)
+
+/**
+ * Expand the length to DWORD alignment with 'Unused' field.
+ *
+ * FLOW RESULT:
+ *  |  Unused | enable (acl) |    uid       |
+ *  |---------+--------------+--------------|
+ *  | 15 bits |    1 bit     |   16 bits    |
+ * MSB              --->                   LSB
+ */
+
+#define IPN3KE_FLOW_RESULT_UNUSED_BITS 15
+#define IPN3KE_FLOW_RESULT_ACL_BITS    1
+#define IPN3KE_FLOW_RESULT_UID_BITS    16
+
+#define IPN3KE_FLOW_RESULT_TOTAL_BITS \
+		(IPN3KE_FLOW_RESULT_UNUSED_BITS + \
+		IPN3KE_FLOW_RESULT_ACL_BITS + \
+		IPN3KE_FLOW_RESULT_UID_BITS)
+
+#define IPN3KE_FLOW_RESULT_ACL_OFFSET \
+		(IPN3KE_FLOW_RESULT_UNUSED_BITS)
+
+#define IPN3KE_FLOW_RESULT_UID_OFFSET \
+		(IPN3KE_FLOW_RESULT_ACL_OFFSET + IPN3KE_FLOW_RESULT_ACL_BITS)
+
+#define IPN3KE_FLOW_RESULT_UID_MAX \
+		((1UL << IPN3KE_FLOW_RESULT_UID_BITS) - 1)
+
+#ifndef BITS_PER_BYTE
+#define BITS_PER_BYTE    8
+#endif
+#define BITS_TO_BYTES(bits) \
+	(((bits) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
+
+struct ipn3ke_flow_rule {
+	uint8_t key[BITS_TO_BYTES(IPN3KE_FLOW_KEY_TOTAL_BITS)];
+	uint8_t result[BITS_TO_BYTES(IPN3KE_FLOW_RESULT_TOTAL_BITS)];
+};
+
+struct rte_flow {
+	TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
+
+	struct ipn3ke_flow_rule rule;
+};
+
+TAILQ_HEAD(ipn3ke_flow_list, rte_flow);
+
+extern const struct rte_flow_ops ipn3ke_flow_ops;
+
+int ipn3ke_flow_init(void *dev);
+
+#endif /* _IPN3KE_FLOW_H_ */
diff --git a/drivers/net/ipn3ke/ipn3ke_logs.h b/drivers/net/ipn3ke/ipn3ke_logs.h
new file mode 100644
index 0000000..dedaece
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_logs.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _IPN3KE_LOGS_H_
+#define _IPN3KE_LOGS_H_
+
+#include <rte_log.h>
+
+extern int ipn3ke_afu_logtype;
+
+#define IPN3KE_AFU_PMD_LOG(level, fmt, args...) \
+	rte_log(RTE_LOG_ ## level, ipn3ke_afu_logtype, "ipn3ke_afu: " fmt, \
+		##args)
+
+#define IPN3KE_AFU_PMD_FUNC_TRACE() IPN3KE_AFU_PMD_LOG(DEBUG, ">>")
+
+#define IPN3KE_AFU_PMD_DEBUG(fmt, args...) \
+	IPN3KE_AFU_PMD_LOG(DEBUG, fmt, ## args)
+
+#define IPN3KE_AFU_PMD_INFO(fmt, args...) \
+	IPN3KE_AFU_PMD_LOG(INFO, fmt, ## args)
+
+#define IPN3KE_AFU_PMD_ERR(fmt, args...) \
+	IPN3KE_AFU_PMD_LOG(ERR, fmt, ## args)
+
+#define IPN3KE_AFU_PMD_WARN(fmt, args...) \
+	IPN3KE_AFU_PMD_LOG(WARNING, fmt, ## args)
+
+#endif /* _IPN3KE_LOGS_H_ */
diff --git a/drivers/net/ipn3ke/ipn3ke_representor.c b/drivers/net/ipn3ke/ipn3ke_representor.c
new file mode 100644
index 0000000..a3d99eb
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_representor.c
@@ -0,0 +1,890 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <stdint.h>
+
+#include <rte_bus_pci.h>
+#include <rte_ethdev.h>
+#include <rte_pci.h>
+#include <rte_malloc.h>
+
+#include <rte_mbuf.h>
+#include <rte_sched.h>
+#include <rte_ethdev_driver.h>
+#include <rte_spinlock.h>
+
+#include <rte_io.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+#include <rte_bus_ifpga.h>
+#include <ifpga_logs.h>
+
+#include "ifpga_rawdev_api.h"
+#include "ipn3ke_tm.h"
+#include "ipn3ke_flow.h"
+#include "ipn3ke_logs.h"
+#include "ipn3ke_ethdev.h"
+
+static int ipn3ke_rpst_scan_num;
+static pthread_t ipn3ke_rpst_scan_thread;
+
+/** Double linked list of representor port. */
+TAILQ_HEAD(ipn3ke_rpst_list, ipn3ke_rpst);
+
+static struct ipn3ke_rpst_list ipn3ke_rpst_list =
+	TAILQ_HEAD_INITIALIZER(ipn3ke_rpst_list);
+
+static rte_spinlock_t ipn3ke_link_notify_list_lk = RTE_SPINLOCK_INITIALIZER;
+
+static void
+ipn3ke_rpst_dev_infos_get(struct rte_eth_dev *ethdev,
+	struct rte_eth_dev_info *dev_info)
+{
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+
+	dev_info->speed_capa =
+		(hw->retimer.mac_type ==
+			IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) ?
+		ETH_LINK_SPEED_10G :
+		((hw->retimer.mac_type ==
+			IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) ?
+		ETH_LINK_SPEED_25G :
+		ETH_LINK_SPEED_AUTONEG);
+
+	dev_info->max_rx_queues  = 1;
+	dev_info->max_tx_queues  = 1;
+	dev_info->min_rx_bufsize = IPN3KE_AFU_BUF_SIZE_MIN;
+	dev_info->max_rx_pktlen  = IPN3KE_AFU_FRAME_SIZE_MAX;
+	dev_info->max_mac_addrs  = hw->port_num;
+	dev_info->max_vfs = 0;
+	dev_info->default_txconf = (struct rte_eth_txconf) {
+		.offloads = 0,
+	};
+	dev_info->rx_queue_offload_capa = 0;
+	dev_info->rx_offload_capa =
+		DEV_RX_OFFLOAD_VLAN_STRIP |
+		DEV_RX_OFFLOAD_QINQ_STRIP |
+		DEV_RX_OFFLOAD_IPV4_CKSUM |
+		DEV_RX_OFFLOAD_UDP_CKSUM |
+		DEV_RX_OFFLOAD_TCP_CKSUM |
+		DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+		DEV_RX_OFFLOAD_VLAN_EXTEND |
+		DEV_RX_OFFLOAD_VLAN_FILTER |
+		DEV_RX_OFFLOAD_JUMBO_FRAME;
+
+	dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
+	dev_info->tx_offload_capa =
+		DEV_TX_OFFLOAD_VLAN_INSERT |
+		DEV_TX_OFFLOAD_QINQ_INSERT |
+		DEV_TX_OFFLOAD_IPV4_CKSUM |
+		DEV_TX_OFFLOAD_UDP_CKSUM |
+		DEV_TX_OFFLOAD_TCP_CKSUM |
+		DEV_TX_OFFLOAD_SCTP_CKSUM |
+		DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+		DEV_TX_OFFLOAD_TCP_TSO |
+		DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
+		DEV_TX_OFFLOAD_GRE_TNL_TSO |
+		DEV_TX_OFFLOAD_IPIP_TNL_TSO |
+		DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
+		DEV_TX_OFFLOAD_MULTI_SEGS |
+		dev_info->tx_queue_offload_capa;
+
+	dev_info->dev_capa =
+		RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
+		RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+
+	dev_info->switch_info.name = ethdev->device->name;
+	dev_info->switch_info.domain_id = rpst->switch_domain_id;
+	dev_info->switch_info.port_id = rpst->port_id;
+}
+
+static int
+ipn3ke_rpst_dev_configure(__rte_unused struct rte_eth_dev *dev)
+{
+	return 0;
+}
+
+static int
+ipn3ke_rpst_dev_start(struct rte_eth_dev *dev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(dev);
+	struct rte_rawdev *rawdev;
+	struct ifpga_rawdev_mac_info mac_info;
+	uint32_t val;
+	char attr_name[IPN3KE_RAWDEV_ATTR_LEN_MAX];
+
+	rawdev = hw->rawdev;
+
+	memset(attr_name, 0, sizeof(attr_name));
+	snprintf(attr_name, IPN3KE_RAWDEV_ATTR_LEN_MAX, "%s",
+			"default_mac");
+	mac_info.port_id = rpst->port_id;
+	rawdev->dev_ops->attr_get(rawdev, attr_name, (uint64_t *)&mac_info);
+	ether_addr_copy(&mac_info.addr, &rpst->mac_addr);
+
+	ether_addr_copy(&mac_info.addr, &dev->data->mac_addrs[0]);
+
+	/* Set mac address */
+	rte_memcpy(((char *)(&val)),
+		(char *)&mac_info.addr.addr_bytes[0],
+		sizeof(uint32_t));
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_PRIMARY_MAC_ADDR0,
+			rpst->port_id,
+			0);
+	rte_memcpy(((char *)(&val)),
+		(char *)&mac_info.addr.addr_bytes[4],
+		sizeof(uint16_t));
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_PRIMARY_MAC_ADDR1,
+			rpst->port_id,
+			0);
+
+	/* Enable the TX path */
+	val = 0;
+	val &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_TX_PACKET_CONTROL,
+			rpst->port_id,
+			0);
+
+	/* Disables source address override */
+	val = 0;
+	val &= IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE,
+			rpst->port_id,
+			0);
+
+	/* Enable the RX path */
+	val = 0;
+	val &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_TRANSFER_CONTROL,
+			rpst->port_id,
+			0);
+
+	/* Clear all TX statistics counters */
+	val = 1;
+	val &= IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_TX_STATS_CLR,
+			rpst->port_id,
+			0);
+
+	/* Clear all RX statistics counters */
+	val = 1;
+	val &= IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_STATS_CLR,
+			rpst->port_id,
+			0);
+
+	return 0;
+}
+
+static void
+ipn3ke_rpst_dev_stop(__rte_unused struct rte_eth_dev *dev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(dev);
+	uint32_t val;
+
+	/* Disable the TX path */
+	val = 1;
+	val &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_TX_PACKET_CONTROL,
+			rpst->port_id,
+			0);
+
+	/* Disable the RX path */
+	val = 1;
+	val &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_TRANSFER_CONTROL,
+			rpst->port_id,
+			0);
+}
+
+static void
+ipn3ke_rpst_dev_close(struct rte_eth_dev *dev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(dev);
+	uint32_t val;
+
+	/* Disable the TX path */
+	val = 1;
+	val &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_TX_PACKET_CONTROL,
+			rpst->port_id,
+			0);
+
+	/* Disable the RX path */
+	val = 1;
+	val &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_TRANSFER_CONTROL,
+			rpst->port_id,
+			0);
+}
+
+/*
+ * Reset PF device only to re-initialize resources in PMD layer
+ */
+static int
+ipn3ke_rpst_dev_reset(struct rte_eth_dev *dev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(dev);
+	uint32_t val;
+
+	/* Disable the TX path */
+	val = 1;
+	val &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_TX_PACKET_CONTROL,
+			rpst->port_id,
+			0);
+
+	/* Disable the RX path */
+	val = 1;
+	val &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_TRANSFER_CONTROL,
+			rpst->port_id,
+			0);
+
+	return 0;
+}
+
+int
+ipn3ke_rpst_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
+{
+	return 0;
+}
+int
+ipn3ke_rpst_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
+{
+	return 0;
+}
+int
+ipn3ke_rpst_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
+{
+	return 0;
+}
+int
+ipn3ke_rpst_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
+{
+	return 0;
+}
+int
+ipn3ke_rpst_rx_queue_setup(struct rte_eth_dev *dev,
+					uint16_t queue_idx,
+					uint16_t nb_desc,
+					unsigned int socket_id,
+					const struct rte_eth_rxconf *rx_conf,
+					struct rte_mempool *mp)
+{
+	return 0;
+}
+void
+ipn3ke_rpst_rx_queue_release(void *rxq)
+{
+}
+int
+ipn3ke_rpst_tx_queue_setup(struct rte_eth_dev *dev,
+					uint16_t queue_idx,
+					uint16_t nb_desc,
+					unsigned int socket_id,
+					const struct rte_eth_txconf *tx_conf)
+{
+	return 0;
+}
+void
+ipn3ke_rpst_tx_queue_release(void *txq)
+{
+}
+
+static int
+ipn3ke_rpst_stats_get(struct rte_eth_dev *ethdev,
+				struct rte_eth_stats *stats)
+{
+	return 0;
+}
+static int
+ipn3ke_rpst_xstats_get(struct rte_eth_dev *dev,
+				struct rte_eth_xstat *xstats,
+				unsigned int n)
+{
+	return 0;
+}
+static int ipn3ke_rpst_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
+		struct rte_eth_xstat_name *xstats_names,
+		__rte_unused unsigned int limit)
+{
+	return 0;
+}
+
+static void
+ipn3ke_rpst_stats_reset(struct rte_eth_dev *ethdev)
+{
+}
+
+static int
+ipn3ke_retimer_conf_link(struct rte_rawdev *rawdev,
+				uint16_t port,
+				uint8_t force_speed,
+				bool is_up)
+{
+	struct ifpga_rawdevg_link_info linfo;
+
+	linfo.port = port;
+	linfo.link_up = is_up;
+	linfo.link_speed = force_speed;
+
+	return rawdev->dev_ops->attr_set(rawdev,
+					"retimer_linkstatus",
+					(uint64_t)&linfo);
+}
+
+static void
+ipn3ke_update_link(struct rte_rawdev *rawdev,
+			uint16_t port,
+			struct rte_eth_link *link)
+{
+	struct ifpga_rawdevg_link_info linfo;
+
+	rawdev->dev_ops->attr_get(rawdev,
+				"retimer_linkstatus",
+				(uint64_t *)&linfo);
+	/* Parse the link status */
+	link->link_status = linfo.link_up;
+	switch (linfo.link_speed) {
+	case IFPGA_RAWDEV_LINK_SPEED_10GB:
+		link->link_speed = ETH_SPEED_NUM_10G;
+		break;
+	case IFPGA_RAWDEV_LINK_SPEED_25GB:
+		link->link_speed = ETH_SPEED_NUM_25G;
+		break;
+	default:
+		IPN3KE_AFU_PMD_LOG(ERR, "Unknown link speed info %u",
+			linfo.link_speed);
+		break;
+	}
+}
+
+/*
+ * Set device link up.
+ */
+int
+ipn3ke_rpst_dev_set_link_up(struct rte_eth_dev *dev)
+{
+	uint8_t link_speed = IFPGA_RAWDEV_LINK_SPEED_UNKNOWN;
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(dev);
+	struct rte_rawdev *rawdev;
+	struct rte_eth_conf *conf = &dev->data->dev_conf;
+
+	rawdev = hw->rawdev;
+	if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
+		conf->link_speeds = ETH_LINK_SPEED_25G |
+				ETH_LINK_SPEED_10G;
+	}
+
+	if (conf->link_speeds & ETH_LINK_SPEED_10G)
+		link_speed = IFPGA_RAWDEV_LINK_SPEED_25GB;
+	else if (conf->link_speeds & ETH_LINK_SPEED_25G)
+		link_speed = IFPGA_RAWDEV_LINK_SPEED_10GB;
+	else
+		link_speed = IFPGA_RAWDEV_LINK_SPEED_UNKNOWN;
+
+	if (rpst->i40e_pf_eth)
+		rte_eth_dev_set_link_up(rpst->i40e_pf_eth_port_id);
+
+	return ipn3ke_retimer_conf_link(rawdev,
+					rpst->port_id,
+					link_speed,
+					true);
+}
+
+/*
+ * Set device link down.
+ */
+int
+ipn3ke_rpst_dev_set_link_down(struct rte_eth_dev *dev)
+{
+	uint8_t link_speed = IFPGA_RAWDEV_LINK_SPEED_UNKNOWN;
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(dev);
+
+	if (rpst->i40e_pf_eth)
+		rte_eth_dev_set_link_down(rpst->i40e_pf_eth_port_id);
+
+	return ipn3ke_retimer_conf_link(hw->rawdev,
+					rpst->port_id,
+					link_speed,
+					false);
+}
+int
+ipn3ke_rpst_link_update(struct rte_eth_dev *ethdev,
+	int wait_to_complete)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	struct rte_rawdev *rawdev;
+	struct rte_eth_link link;
+	int ret;
+
+	memset(&link, 0, sizeof(link));
+
+	link.link_duplex = ETH_LINK_FULL_DUPLEX;
+	link.link_autoneg = !(ethdev->data->dev_conf.link_speeds &
+				ETH_LINK_SPEED_FIXED);
+
+	rawdev = hw->rawdev;
+	ipn3ke_update_link(rawdev, rpst->port_id, &link);
+
+	if (rpst->i40e_pf_eth &&
+		!rpst->ori_linfo.link_status &&
+		link.link_status)
+		rte_eth_dev_set_link_up(rpst->i40e_pf_eth_port_id);
+	else if ((rpst->i40e_pf_eth != NULL) &&
+		rpst->ori_linfo.link_status &&
+		!link.link_status)
+		rte_eth_dev_set_link_down(rpst->i40e_pf_eth_port_id);
+
+	rpst->ori_linfo.link_status = link.link_status;
+	rpst->ori_linfo.link_speed = link.link_speed;
+
+	ret = rte_eth_linkstatus_set(ethdev, &link);
+	if (rpst->i40e_pf_eth)
+		ret = rte_eth_linkstatus_set(rpst->i40e_pf_eth, &link);
+
+	return ret;
+}
+
+static int
+ipn3ke_rpst_link_update1(struct ipn3ke_rpst *rpst)
+{
+	struct ipn3ke_hw *hw;
+	struct rte_rawdev *rawdev;
+	struct rte_eth_link link;
+	int ret = 0;
+
+	if (!rpst)
+		return -1;
+
+	hw = rpst->hw;
+
+	memset(&link, 0, sizeof(link));
+
+	rawdev = hw->rawdev;
+	ipn3ke_update_link(rawdev, rpst->port_id, &link);
+
+	if (rpst->i40e_pf_eth &&
+		!rpst->ori_linfo.link_status &&
+		link.link_status)
+		rte_eth_dev_set_link_up(rpst->i40e_pf_eth_port_id);
+	else if ((rpst->i40e_pf_eth != NULL) &&
+		rpst->ori_linfo.link_status &&
+		!link.link_status)
+		rte_eth_dev_set_link_down(rpst->i40e_pf_eth_port_id);
+
+	rpst->ori_linfo.link_status = link.link_status;
+	rpst->ori_linfo.link_speed = link.link_speed;
+
+	if (rpst->i40e_pf_eth)
+		ret = rte_eth_linkstatus_set(rpst->i40e_pf_eth, &link);
+
+	return ret;
+}
+
+static void *
+ipn3ke_rpst_scan_handle_request(void *param)
+{
+	struct ipn3ke_rpst *rpst;
+	int num = 0;
+#define MS 1000
+#define SCAN_NUM 32
+
+	for (;;) {
+		num = 0;
+		TAILQ_FOREACH(rpst, &ipn3ke_rpst_list, next) {
+			if (rpst->i40e_pf_eth)
+				ipn3ke_rpst_link_update1(rpst);
+
+			if (++num > SCAN_NUM)
+				usleep(1 * MS);
+		}
+		usleep(50 * MS);
+
+		if (num == 0xffffff)
+			return NULL;
+	}
+
+	return NULL;
+}
+static int
+ipn3ke_rpst_scan_check(void)
+{
+	int ret;
+
+	if (ipn3ke_rpst_scan_num == 1) {
+		ret = pthread_create(&ipn3ke_rpst_scan_thread,
+			NULL,
+			ipn3ke_rpst_scan_handle_request, NULL);
+		if (ret) {
+			IPN3KE_AFU_PMD_ERR("Fail to create ipn3ke rpst scan thread");
+			return -1;
+		}
+	} else if (ipn3ke_rpst_scan_num == 0) {
+		ret = pthread_cancel(ipn3ke_rpst_scan_thread);
+		if (ret)
+			IPN3KE_AFU_PMD_ERR("Can't cancel the thread");
+
+		ret = pthread_join(ipn3ke_rpst_scan_thread, NULL);
+		if (ret)
+			IPN3KE_AFU_PMD_ERR("Can't join the thread");
+
+		return ret;
+	}
+
+	return 0;
+}
+
+void
+ipn3ke_rpst_promiscuous_enable(struct rte_eth_dev *ethdev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	uint32_t rddata, val;
+
+	/* Enable all unicast */
+	(*hw->f_mac_read)(hw,
+			&rddata,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+	val = 1;
+	val &= IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_MASK;
+	val |= rddata;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+}
+
+void
+ipn3ke_rpst_promiscuous_disable(struct rte_eth_dev *ethdev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	uint32_t rddata, val;
+
+	/* Disable all unicast */
+	(*hw->f_mac_read)(hw,
+			&rddata,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+	val = 0;
+	val &= IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_MASK;
+	val |= rddata;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+}
+
+void
+ipn3ke_rpst_allmulticast_enable(struct rte_eth_dev *ethdev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	uint32_t rddata, val;
+
+	/* Enable all unicast */
+	(*hw->f_mac_read)(hw,
+			&rddata,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+	val = 1;
+	val <<= IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT;
+	val &= IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_MASK;
+	val |= rddata;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+}
+
+void
+ipn3ke_rpst_allmulticast_disable(struct rte_eth_dev *ethdev)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	uint32_t rddata, val;
+
+	/* Disable all unicast */
+	(*hw->f_mac_read)(hw,
+			&rddata,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+	val = 0;
+	val <<= IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT;
+	val &= IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_MASK;
+	val |= rddata;
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_RX_FRAME_CONTROL,
+			rpst->port_id,
+			0);
+}
+
+int
+ipn3ke_rpst_mac_addr_set(struct rte_eth_dev *ethdev,
+				struct ether_addr *mac_addr)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	uint32_t val;
+
+	if (!is_valid_assigned_ether_addr(mac_addr)) {
+		IPN3KE_AFU_PMD_LOG(ERR, "Tried to set invalid MAC address.");
+		return -EINVAL;
+	}
+
+	ether_addr_copy(&mac_addr[0], &rpst->mac_addr);
+
+	/* Set mac address */
+	rte_memcpy(((char *)(&val)), &mac_addr[0], sizeof(uint32_t));
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_PRIMARY_MAC_ADDR0,
+			rpst->port_id,
+			0);
+	rte_memcpy(((char *)(&val)), &mac_addr[4], sizeof(uint16_t));
+	(*hw->f_mac_write)(hw,
+			val,
+			IPN3KE_MAC_PRIMARY_MAC_ADDR0,
+			rpst->port_id,
+			0);
+
+	return 0;
+}
+int
+ipn3ke_rpst_mtu_set(struct rte_eth_dev *ethdev, uint16_t mtu)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	uint32_t frame_size = mtu;
+
+	/* check if mtu is within the allowed range */
+	if ((frame_size < ETHER_MIN_MTU) ||
+		(frame_size > IPN3KE_MAC_FRAME_SIZE_MAX))
+		return -EINVAL;
+
+	frame_size &= IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK;
+	(*hw->f_mac_write)(hw,
+			frame_size,
+			IPN3KE_MAC_RX_FRAME_MAXLENGTH,
+			rpst->port_id,
+			0);
+
+	if (rpst->i40e_pf_eth)
+		rpst->i40e_pf_eth->dev_ops->mtu_set(rpst->i40e_pf_eth, mtu);
+
+	return 0;
+}
+
+static int
+ipn3ke_afu_filter_ctrl(struct rte_eth_dev *ethdev,
+				enum rte_filter_type filter_type,
+				enum rte_filter_op filter_op,
+				void *arg)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	int ret = 0;
+
+	if (ethdev == NULL)
+		return -EINVAL;
+
+	if (hw->acc_flow)
+		switch (filter_type) {
+		case RTE_ETH_FILTER_GENERIC:
+			if (filter_op != RTE_ETH_FILTER_GET)
+				return -EINVAL;
+			*(const void **)arg = &ipn3ke_flow_ops;
+			break;
+		default:
+			IPN3KE_AFU_PMD_WARN("Filter type (%d) not supported",
+					filter_type);
+			ret = -EINVAL;
+			break;
+		}
+	else if (rpst->i40e_pf_eth)
+		(*rpst->i40e_pf_eth->dev_ops->filter_ctrl)(ethdev,
+							filter_type,
+							filter_op,
+							arg);
+	else
+		return -EINVAL;
+
+	return ret;
+}
+
+struct eth_dev_ops ipn3ke_rpst_dev_ops = {
+	.dev_infos_get        = ipn3ke_rpst_dev_infos_get,
+
+	.dev_configure        = ipn3ke_rpst_dev_configure,
+	.dev_start            = ipn3ke_rpst_dev_start,
+	.dev_stop             = ipn3ke_rpst_dev_stop,
+	.dev_close            = ipn3ke_rpst_dev_close,
+	.dev_reset            = ipn3ke_rpst_dev_reset,
+
+	.stats_get            = ipn3ke_rpst_stats_get,
+	.xstats_get           = ipn3ke_rpst_xstats_get,
+	.xstats_get_names     = ipn3ke_rpst_xstats_get_names,
+	.stats_reset          = ipn3ke_rpst_stats_reset,
+	.xstats_reset         = ipn3ke_rpst_stats_reset,
+
+	.filter_ctrl          = ipn3ke_afu_filter_ctrl,
+
+	.rx_queue_start       = ipn3ke_rpst_rx_queue_start,
+	.rx_queue_stop        = ipn3ke_rpst_rx_queue_stop,
+	.tx_queue_start       = ipn3ke_rpst_tx_queue_start,
+	.tx_queue_stop        = ipn3ke_rpst_tx_queue_stop,
+	.rx_queue_setup       = ipn3ke_rpst_rx_queue_setup,
+	.rx_queue_release     = ipn3ke_rpst_rx_queue_release,
+	.tx_queue_setup       = ipn3ke_rpst_tx_queue_setup,
+	.tx_queue_release     = ipn3ke_rpst_tx_queue_release,
+
+	.dev_set_link_up      = ipn3ke_rpst_dev_set_link_up,
+	.dev_set_link_down    = ipn3ke_rpst_dev_set_link_down,
+	.link_update          = ipn3ke_rpst_link_update,
+
+	.promiscuous_enable   = ipn3ke_rpst_promiscuous_enable,
+	.promiscuous_disable  = ipn3ke_rpst_promiscuous_disable,
+	.allmulticast_enable  = ipn3ke_rpst_allmulticast_enable,
+	.allmulticast_disable = ipn3ke_rpst_allmulticast_disable,
+	.mac_addr_set         = ipn3ke_rpst_mac_addr_set,
+	/*.get_reg              = ipn3ke_get_regs,*/
+	.mtu_set              = ipn3ke_rpst_mtu_set,
+
+	/**
+	 * .rxq_info_get         = ipn3ke_rxq_info_get,
+	 * .txq_info_get         = ipn3ke_txq_info_get,
+	 * .fw_version_get       = ,
+	 * .get_module_info      = ipn3ke_get_module_info,
+	 */
+
+	.tm_ops_get           = ipn3ke_tm_ops_get,
+};
+
+static uint16_t ipn3ke_rpst_recv_pkts(void *rx_q,
+		struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
+{
+	return 0;
+}
+
+static uint16_t
+ipn3ke_rpst_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
+	uint16_t nb_pkts)
+{
+	return 0;
+}
+
+int
+ipn3ke_rpst_init(struct rte_eth_dev *ethdev, void *init_params)
+{
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	struct ipn3ke_rpst *representor_param =
+			(struct ipn3ke_rpst *)init_params;
+
+	if (representor_param->port_id >= representor_param->hw->port_num)
+		return -ENODEV;
+
+	rpst->switch_domain_id = representor_param->switch_domain_id;
+	rpst->port_id = representor_param->port_id;
+	rpst->hw = representor_param->hw;
+	rpst->i40e_pf_eth = NULL;
+	rpst->i40e_pf_eth_port_id = 0xFFFF;
+
+	if (rpst->hw->tm_hw_enable)
+		ipn3ke_tm_init(rpst);
+
+	/** representor shares the same driver as it's PF device */
+	/**
+	 * ethdev->device->driver = rpst->hw->eth_dev->device->driver;
+	 */
+
+	/* Set representor device ops */
+	ethdev->dev_ops = &ipn3ke_rpst_dev_ops;
+
+	/* No data-path, but need stub Rx/Tx functions to avoid crash
+	 * when testing with the likes of testpmd.
+	 */
+	ethdev->rx_pkt_burst = ipn3ke_rpst_recv_pkts;
+	ethdev->tx_pkt_burst = ipn3ke_rpst_xmit_pkts;
+
+	ethdev->data->nb_rx_queues = 1;
+	ethdev->data->nb_tx_queues = 1;
+
+	ethdev->data->mac_addrs = rte_zmalloc("ipn3ke_afu_representor",
+						ETHER_ADDR_LEN,
+						0);
+	if (!ethdev->data->mac_addrs) {
+		IPN3KE_AFU_PMD_ERR(
+			"Failed to allocated memory for storing mac address");
+		return -ENODEV;
+	}
+
+	ethdev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
+
+	rte_spinlock_lock(&ipn3ke_link_notify_list_lk);
+	TAILQ_INSERT_TAIL(&ipn3ke_rpst_list, rpst, next);
+	ipn3ke_rpst_scan_num++;
+	ipn3ke_rpst_scan_check();
+	rte_spinlock_unlock(&ipn3ke_link_notify_list_lk);
+
+	return 0;
+}
+
+int
+ipn3ke_rpst_uninit(struct rte_eth_dev *ethdev)
+{
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+
+	rte_spinlock_lock(&ipn3ke_link_notify_list_lk);
+	TAILQ_REMOVE(&ipn3ke_rpst_list, rpst, next);
+	ipn3ke_rpst_scan_num--;
+	ipn3ke_rpst_scan_check();
+	rte_spinlock_unlock(&ipn3ke_link_notify_list_lk);
+
+	return 0;
+}
diff --git a/drivers/net/ipn3ke/ipn3ke_tm.c b/drivers/net/ipn3ke/ipn3ke_tm.c
new file mode 100644
index 0000000..efd7154
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_tm.c
@@ -0,0 +1,2217 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <rte_bus_pci.h>
+#include <rte_ethdev.h>
+#include <rte_pci.h>
+#include <rte_malloc.h>
+#include <rte_tm_driver.h>
+
+#include <rte_mbuf.h>
+#include <rte_sched.h>
+#include <rte_ethdev_driver.h>
+
+#include <rte_io.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+#include <rte_bus_ifpga.h>
+#include <ifpga_logs.h>
+
+#include "ifpga_rawdev_api.h"
+#include "ipn3ke_tm.h"
+#include "ipn3ke_flow.h"
+#include "ipn3ke_logs.h"
+#include "ipn3ke_ethdev.h"
+
+#define BYTES_IN_MBPS     (1000 * 1000 / 8)
+#define SUBPORT_TC_PERIOD 10
+#define PIPE_TC_PERIOD    40
+
+struct ipn3ke_tm_shaper_params_range_type {
+	uint32_t m1;
+	uint32_t m2;
+	uint32_t exp;
+	uint32_t exp2;
+	uint32_t low;
+	uint32_t high;
+};
+struct ipn3ke_tm_shaper_params_range_type ipn3ke_tm_shaper_params_rang[] = {
+	{  0,       1,     0,        1,           0,            4},
+	{  2,       3,     0,        1,           8,           12},
+	{  4,       7,     0,        1,          16,           28},
+	{  8,      15,     0,        1,          32,           60},
+	{ 16,      31,     0,        1,          64,          124},
+	{ 32,      63,     0,        1,         128,          252},
+	{ 64,     127,     0,        1,         256,          508},
+	{128,     255,     0,        1,         512,         1020},
+	{256,     511,     0,        1,        1024,         2044},
+	{512,    1023,     0,        1,        2048,         4092},
+	{512,    1023,     1,        2,        4096,         8184},
+	{512,    1023,     2,        4,        8192,        16368},
+	{512,    1023,     3,        8,       16384,        32736},
+	{512,    1023,     4,       16,       32768,        65472},
+	{512,    1023,     5,       32,       65536,       130944},
+	{512,    1023,     6,       64,      131072,       261888},
+	{512,    1023,     7,      128,      262144,       523776},
+	{512,    1023,     8,      256,      524288,      1047552},
+	{512,    1023,     9,      512,     1048576,      2095104},
+	{512,    1023,    10,     1024,     2097152,      4190208},
+	{512,    1023,    11,     2048,     4194304,      8380416},
+	{512,    1023,    12,     4096,     8388608,     16760832},
+	{512,    1023,    13,     8192,    16777216,     33521664},
+	{512,    1023,    14,    16384,    33554432,     67043328},
+	{512,    1023,    15,    32768,    67108864,    134086656},
+};
+
+#define IPN3KE_TM_SHAPER_RANGE_NUM (sizeof(ipn3ke_tm_shaper_params_rang) / \
+	sizeof(struct ipn3ke_tm_shaper_params_range_type))
+
+#define IPN3KE_TM_SHAPER_COMMITTED_RATE_MAX \
+	(ipn3ke_tm_shaper_params_rang[IPN3KE_TM_SHAPER_RANGE_NUM - 1].high)
+
+#define IPN3KE_TM_SHAPER_PEAK_RATE_MAX \
+	(ipn3ke_tm_shaper_params_rang[IPN3KE_TM_SHAPER_RANGE_NUM - 1].high)
+
+int
+ipn3ke_hw_tm_init(struct ipn3ke_hw *hw)
+{
+#define SCRATCH_DATA 0xABCDEF
+	struct ipn3ke_tm_node *nodes;
+	struct ipn3ke_tm_tdrop_profile *tdrop_profile;
+	int node_num;
+	int i;
+
+	if (hw == NULL)
+		return -EINVAL;
+#if IPN3KE_TM_SCRATCH_RW
+	uint32_t scratch_data;
+	IPN3KE_MASK_WRITE_REG(hw,
+					IPN3KE_TM_SCRATCH,
+					0,
+					SCRATCH_DATA,
+					0xFFFFFFFF);
+	scratch_data = IPN3KE_MASK_READ_REG(hw,
+					IPN3KE_TM_SCRATCH,
+					0,
+					0xFFFFFFFF);
+	if (scratch_data != SCRATCH_DATA)
+		return -EINVAL;
+#endif
+	/* alloc memory for all hierarchy nodes */
+	node_num = hw->port_num +
+		IPN3KE_TM_VT_NODE_NUM +
+		IPN3KE_TM_COS_NODE_NUM;
+
+	nodes = rte_zmalloc("ipn3ke_tm_nodes",
+			sizeof(struct ipn3ke_tm_node) * node_num,
+			0);
+	if (!nodes)
+		return -ENOMEM;
+
+	/* alloc memory for Tail Drop Profile */
+	tdrop_profile = rte_zmalloc("ipn3ke_tm_tdrop_profile",
+				sizeof(struct ipn3ke_tm_tdrop_profile) *
+				IPN3KE_TM_TDROP_PROFILE_NUM,
+				0);
+	if (!tdrop_profile) {
+		rte_free(nodes);
+		return -ENOMEM;
+	}
+
+	hw->nodes = nodes;
+	hw->port_nodes = nodes;
+	hw->vt_nodes = hw->port_nodes + hw->port_num;
+	hw->cos_nodes = hw->vt_nodes + IPN3KE_TM_VT_NODE_NUM;
+	hw->tdrop_profile = tdrop_profile;
+	hw->tdrop_profile_num = IPN3KE_TM_TDROP_PROFILE_NUM;
+
+	for (i = 0, nodes = hw->port_nodes;
+		i < hw->port_num;
+		i++, nodes++) {
+		nodes->node_index = i;
+		nodes->level = IPN3KE_TM_NODE_LEVEL_PORT;
+		nodes->tm_id = RTE_TM_NODE_ID_NULL;
+		nodes->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+		nodes->parent_node_id = RTE_TM_NODE_ID_NULL;
+		nodes->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+		nodes->weight = 0;
+		nodes->parent_node = NULL;
+		nodes->shaper_profile.valid = 0;
+		nodes->tdrop_profile = NULL;
+		nodes->n_children = 0;
+		TAILQ_INIT(&nodes->children_node_list);
+	}
+
+	for (i = 0, nodes = hw->vt_nodes;
+		i < IPN3KE_TM_VT_NODE_NUM;
+		i++, nodes++) {
+		nodes->node_index = i;
+		nodes->level = IPN3KE_TM_NODE_LEVEL_VT;
+		nodes->tm_id = RTE_TM_NODE_ID_NULL;
+		nodes->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+		nodes->parent_node_id = RTE_TM_NODE_ID_NULL;
+		nodes->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+		nodes->weight = 0;
+		nodes->parent_node = NULL;
+		nodes->shaper_profile.valid = 0;
+		nodes->tdrop_profile = NULL;
+		nodes->n_children = 0;
+		TAILQ_INIT(&nodes->children_node_list);
+	}
+
+	for (i = 0, nodes = hw->cos_nodes;
+		i < IPN3KE_TM_COS_NODE_NUM;
+		i++, nodes++) {
+		nodes->node_index = i;
+		nodes->level = IPN3KE_TM_NODE_LEVEL_COS;
+		nodes->tm_id = RTE_TM_NODE_ID_NULL;
+		nodes->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+		nodes->parent_node_id = RTE_TM_NODE_ID_NULL;
+		nodes->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+		nodes->weight = 0;
+		nodes->parent_node = NULL;
+		nodes->shaper_profile.valid = 0;
+		nodes->tdrop_profile = NULL;
+		nodes->n_children = 0;
+		TAILQ_INIT(&nodes->children_node_list);
+	}
+
+	for (i = 0, tdrop_profile = hw->tdrop_profile;
+		i < IPN3KE_TM_TDROP_PROFILE_NUM;
+		i++, tdrop_profile++) {
+		tdrop_profile->tdrop_profile_id = i;
+		tdrop_profile->n_users = 0;
+		tdrop_profile->valid = 0;
+	}
+
+	return 0;
+}
+void
+ipn3ke_tm_init(struct ipn3ke_rpst *rpst)
+{
+	struct ipn3ke_tm_internals *tm;
+	struct ipn3ke_tm_node *port_node;
+
+	tm = &rpst->tm;
+
+	port_node = &rpst->hw->port_nodes[rpst->port_id];
+	tm->h.port_node = port_node;
+
+	tm->h.n_shaper_profiles = 0;
+	tm->h.n_tdrop_profiles = 0;
+	tm->h.n_vt_nodes = 0;
+	tm->h.n_cos_nodes = 0;
+
+	tm->h.port_commit_node = NULL;
+	TAILQ_INIT(&tm->h.vt_commit_node_list);
+	TAILQ_INIT(&tm->h.cos_commit_node_list);
+
+	tm->hierarchy_frozen = 0;
+	tm->tm_started = 1;
+	tm->tm_id = rpst->port_id;
+}
+
+static struct ipn3ke_tm_shaper_profile *
+ipn3ke_hw_tm_shaper_profile_search(struct ipn3ke_hw *hw,
+						uint32_t shaper_profile_id,
+						struct rte_tm_error *error)
+{
+	struct ipn3ke_tm_shaper_profile *sp = NULL;
+	uint32_t level_of_node_id;
+	uint32_t node_index;
+
+	/* Shaper profile ID must not be NONE. */
+	if (shaper_profile_id == RTE_TM_SHAPER_PROFILE_ID_NONE) {
+		rte_tm_error_set(error,
+				EINVAL,
+				RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+				NULL,
+				rte_strerror(EINVAL));
+
+		return NULL;
+	}
+
+	level_of_node_id = shaper_profile_id / IPN3KE_TM_NODE_LEVEL_MOD;
+	node_index = shaper_profile_id % IPN3KE_TM_NODE_LEVEL_MOD;
+
+	switch (level_of_node_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		if (node_index >= hw->port_num)
+			rte_tm_error_set(error,
+					EEXIST,
+					RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+					NULL,
+					rte_strerror(EEXIST));
+		else
+			sp = &hw->port_nodes[node_index].shaper_profile;
+
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		if (node_index >= IPN3KE_TM_VT_NODE_NUM)
+			rte_tm_error_set(error,
+					EEXIST,
+					RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+					NULL,
+					rte_strerror(EEXIST));
+		else
+			sp = &hw->vt_nodes[node_index].shaper_profile;
+
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		if (node_index >= IPN3KE_TM_COS_NODE_NUM)
+			rte_tm_error_set(error,
+					EEXIST,
+					RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+					NULL,
+					rte_strerror(EEXIST));
+		else
+			sp = &hw->cos_nodes[node_index].shaper_profile;
+
+		break;
+	default:
+		rte_tm_error_set(error,
+				EEXIST,
+				RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+				NULL,
+				rte_strerror(EEXIST));
+	}
+
+	return sp;
+}
+
+static struct ipn3ke_tm_tdrop_profile *
+ipn3ke_hw_tm_tdrop_profile_search(struct ipn3ke_hw *hw,
+	uint32_t tdrop_profile_id)
+{
+	struct ipn3ke_tm_tdrop_profile *tdrop_profile;
+
+	if (tdrop_profile_id >= hw->tdrop_profile_num)
+		return NULL;
+
+	tdrop_profile = &hw->tdrop_profile[tdrop_profile_id];
+	if (tdrop_profile->valid)
+		return tdrop_profile;
+
+	return NULL;
+}
+
+static struct ipn3ke_tm_node *
+ipn3ke_hw_tm_node_search(struct ipn3ke_hw *hw, uint32_t tm_id,
+	uint32_t node_id, uint32_t state_mask)
+{
+	uint32_t level_of_node_id;
+	uint32_t node_index;
+	struct ipn3ke_tm_node *n;
+
+	level_of_node_id = node_id / IPN3KE_TM_NODE_LEVEL_MOD;
+	node_index = node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+
+	switch (level_of_node_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		if (node_index >= hw->port_num)
+			return NULL;
+		n = &hw->port_nodes[node_index];
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		if (node_index >= IPN3KE_TM_VT_NODE_NUM)
+			return NULL;
+		n = &hw->vt_nodes[node_index];
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		if (node_index >= IPN3KE_TM_COS_NODE_NUM)
+			return NULL;
+		n = &hw->cos_nodes[node_index];
+
+		break;
+	default:
+		return NULL;
+	}
+
+	/* Check tm node status */
+	if (n->node_state == IPN3KE_TM_NODE_STATE_IDLE) {
+		if ((n->tm_id != RTE_TM_NODE_ID_NULL) ||
+		(n->parent_node_id != RTE_TM_NODE_ID_NULL) ||
+		(n->parent_node != NULL) ||
+		(n->n_children > 0)) {
+			IPN3KE_ASSERT(0);
+			IPN3KE_AFU_PMD_LOG(WARNING,
+				"tm node check error %d", 1);
+		}
+	} else if (n->node_state < IPN3KE_TM_NODE_STATE_MAX) {
+		if ((n->tm_id == RTE_TM_NODE_ID_NULL) ||
+		((level_of_node_id != IPN3KE_TM_NODE_LEVEL_PORT) &&
+			(n->parent_node_id == RTE_TM_NODE_ID_NULL)) ||
+		((level_of_node_id != IPN3KE_TM_NODE_LEVEL_PORT) &&
+			(n->parent_node == NULL))) {
+			IPN3KE_ASSERT(0);
+			IPN3KE_AFU_PMD_LOG(WARNING,
+				"tm node check error %d", 1);
+		}
+	} else {
+		IPN3KE_ASSERT(0);
+			IPN3KE_AFU_PMD_LOG(WARNING,
+				"tm node check error %d", 1);
+	}
+
+	if (IPN3KE_BIT_ISSET(state_mask, n->node_state)) {
+		if (n->node_state == IPN3KE_TM_NODE_STATE_IDLE)
+			return n;
+		else if (n->tm_id == tm_id)
+			return n;
+		else
+			return NULL;
+	} else
+		return NULL;
+}
+
+/* Traffic manager node type get */
+static int
+ipn3ke_pmd_tm_node_type_get(struct rte_eth_dev *dev,
+	uint32_t node_id,
+	int *is_leaf,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	uint32_t tm_id;
+	struct ipn3ke_tm_node *node;
+	uint32_t state_mask;
+
+	if (is_leaf == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_UNSPECIFIED,
+					NULL,
+					rte_strerror(EINVAL));
+
+	tm_id = tm->tm_id;
+
+	state_mask = 0;
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_COMMITTED);
+	node = ipn3ke_hw_tm_node_search(hw, tm_id, node_id, state_mask);
+	if (node_id == RTE_TM_NODE_ID_NULL ||
+		(node == NULL))
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	*is_leaf = (node->level == IPN3KE_TM_NODE_LEVEL_COS) ? 1 : 0;
+
+	return 0;
+}
+
+#define WRED_SUPPORTED    0
+
+#define STATS_MASK_DEFAULT \
+	(RTE_TM_STATS_N_PKTS | \
+	RTE_TM_STATS_N_BYTES | \
+	RTE_TM_STATS_N_PKTS_GREEN_DROPPED | \
+	RTE_TM_STATS_N_BYTES_GREEN_DROPPED)
+
+#define STATS_MASK_QUEUE \
+	(STATS_MASK_DEFAULT | RTE_TM_STATS_N_PKTS_QUEUED)
+
+/* Traffic manager capabilities get */
+static int
+ipn3ke_tm_capabilities_get(struct rte_eth_dev *dev,
+	struct rte_tm_capabilities *cap,
+	struct rte_tm_error *error)
+{
+	if (cap == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_CAPABILITIES,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* set all the parameters to 0 first. */
+	memset(cap, 0, sizeof(*cap));
+
+	cap->n_nodes_max = 1 + IPN3KE_TM_COS_NODE_NUM + IPN3KE_TM_VT_NODE_NUM;
+	cap->n_levels_max = IPN3KE_TM_NODE_LEVEL_MAX;
+
+	cap->non_leaf_nodes_identical = 0;
+	cap->leaf_nodes_identical = 1;
+
+	cap->shaper_n_max = 1 + IPN3KE_TM_VT_NODE_NUM;
+	cap->shaper_private_n_max = 1 + IPN3KE_TM_VT_NODE_NUM;
+	cap->shaper_private_dual_rate_n_max = 0;
+	cap->shaper_private_rate_min = 1;
+	cap->shaper_private_rate_max = 1 + IPN3KE_TM_VT_NODE_NUM;
+
+	cap->shaper_shared_n_max = 0;
+	cap->shaper_shared_n_nodes_per_shaper_max = 0;
+	cap->shaper_shared_n_shapers_per_node_max = 0;
+	cap->shaper_shared_dual_rate_n_max = 0;
+	cap->shaper_shared_rate_min = 0;
+	cap->shaper_shared_rate_max = 0;
+
+	cap->shaper_pkt_length_adjust_min = RTE_TM_ETH_FRAMING_OVERHEAD_FCS;
+	cap->shaper_pkt_length_adjust_max = RTE_TM_ETH_FRAMING_OVERHEAD_FCS;
+
+	cap->sched_n_children_max = IPN3KE_TM_COS_NODE_NUM;
+	cap->sched_sp_n_priorities_max = 3;
+	cap->sched_wfq_n_children_per_group_max = UINT32_MAX;
+	cap->sched_wfq_n_groups_max = 1;
+	cap->sched_wfq_weight_max = UINT32_MAX;
+
+	cap->cman_wred_packet_mode_supported = 0;
+	cap->cman_wred_byte_mode_supported = 0;
+	cap->cman_head_drop_supported = 0;
+	cap->cman_wred_context_n_max = 0;
+	cap->cman_wred_context_private_n_max = 0;
+	cap->cman_wred_context_shared_n_max = 0;
+	cap->cman_wred_context_shared_n_nodes_per_context_max = 0;
+	cap->cman_wred_context_shared_n_contexts_per_node_max = 0;
+
+	/**
+	 * cap->mark_vlan_dei_supported = {0, 0, 0};
+	 * cap->mark_ip_ecn_tcp_supported = {0, 0, 0};
+	 * cap->mark_ip_ecn_sctp_supported = {0, 0, 0};
+	 * cap->mark_ip_dscp_supported = {0, 0, 0};
+	 */
+
+	cap->dynamic_update_mask = 0;
+
+	cap->stats_mask = 0;
+
+	return 0;
+}
+
+/* Traffic manager level capabilities get */
+static int
+ipn3ke_tm_level_capabilities_get(struct rte_eth_dev *dev,
+	uint32_t level_id,
+	struct rte_tm_level_capabilities *cap,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+
+	if (cap == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_CAPABILITIES,
+					NULL,
+					rte_strerror(EINVAL));
+
+	if (level_id >= IPN3KE_TM_NODE_LEVEL_MAX)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_LEVEL_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* set all the parameters to 0 first. */
+	memset(cap, 0, sizeof(*cap));
+
+	switch (level_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		cap->n_nodes_max = hw->port_num;
+		cap->n_nodes_nonleaf_max = IPN3KE_TM_VT_NODE_NUM;
+		cap->n_nodes_leaf_max = 0;
+		cap->non_leaf_nodes_identical = 0;
+		cap->leaf_nodes_identical = 0;
+
+		cap->nonleaf.shaper_private_supported = 0;
+		cap->nonleaf.shaper_private_dual_rate_supported = 0;
+		cap->nonleaf.shaper_private_rate_min = 1;
+		cap->nonleaf.shaper_private_rate_max = UINT32_MAX;
+		cap->nonleaf.shaper_shared_n_max = 0;
+
+		cap->nonleaf.sched_n_children_max = IPN3KE_TM_VT_NODE_NUM;
+		cap->nonleaf.sched_sp_n_priorities_max = 1;
+		cap->nonleaf.sched_wfq_n_children_per_group_max = 0;
+		cap->nonleaf.sched_wfq_n_groups_max = 0;
+		cap->nonleaf.sched_wfq_weight_max = 0;
+
+		cap->nonleaf.stats_mask = STATS_MASK_DEFAULT;
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		cap->n_nodes_max = IPN3KE_TM_VT_NODE_NUM;
+		cap->n_nodes_nonleaf_max = IPN3KE_TM_COS_NODE_NUM;
+		cap->n_nodes_leaf_max = 0;
+		cap->non_leaf_nodes_identical = 0;
+		cap->leaf_nodes_identical = 0;
+
+		cap->nonleaf.shaper_private_supported = 0;
+		cap->nonleaf.shaper_private_dual_rate_supported = 0;
+		cap->nonleaf.shaper_private_rate_min = 1;
+		cap->nonleaf.shaper_private_rate_max = UINT32_MAX;
+		cap->nonleaf.shaper_shared_n_max = 0;
+
+		cap->nonleaf.sched_n_children_max = IPN3KE_TM_COS_NODE_NUM;
+		cap->nonleaf.sched_sp_n_priorities_max = 1;
+		cap->nonleaf.sched_wfq_n_children_per_group_max = 0;
+		cap->nonleaf.sched_wfq_n_groups_max = 0;
+		cap->nonleaf.sched_wfq_weight_max = 0;
+
+		cap->nonleaf.stats_mask = STATS_MASK_DEFAULT;
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		cap->n_nodes_max = IPN3KE_TM_COS_NODE_NUM;
+		cap->n_nodes_nonleaf_max = 0;
+		cap->n_nodes_leaf_max = IPN3KE_TM_COS_NODE_NUM;
+		cap->non_leaf_nodes_identical = 0;
+		cap->leaf_nodes_identical = 0;
+
+		cap->leaf.shaper_private_supported = 0;
+		cap->leaf.shaper_private_dual_rate_supported = 0;
+		cap->leaf.shaper_private_rate_min = 0;
+		cap->leaf.shaper_private_rate_max = 0;
+		cap->leaf.shaper_shared_n_max = 0;
+
+		cap->leaf.cman_head_drop_supported = 0;
+		cap->leaf.cman_wred_packet_mode_supported = WRED_SUPPORTED;
+		cap->leaf.cman_wred_byte_mode_supported = 0;
+		cap->leaf.cman_wred_context_private_supported = WRED_SUPPORTED;
+		cap->leaf.cman_wred_context_shared_n_max = 0;
+
+		cap->leaf.stats_mask = STATS_MASK_QUEUE;
+		break;
+
+	default:
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_LEVEL_ID,
+					NULL,
+					rte_strerror(EINVAL));
+		break;
+	}
+
+	return 0;
+}
+
+/* Traffic manager node capabilities get */
+static int
+ipn3ke_tm_node_capabilities_get(struct rte_eth_dev *dev,
+	uint32_t node_id,
+	struct rte_tm_node_capabilities *cap,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_rpst *representor = IPN3KE_DEV_PRIVATE_TO_RPST(dev);
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	uint32_t tm_id;
+	struct ipn3ke_tm_node *tm_node;
+	uint32_t state_mask;
+
+	if (cap == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_CAPABILITIES,
+					NULL,
+					rte_strerror(EINVAL));
+
+	tm_id = tm->tm_id;
+
+	state_mask = 0;
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_COMMITTED);
+	tm_node = ipn3ke_hw_tm_node_search(hw, tm_id, node_id, state_mask);
+	if (tm_node == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	if (tm_node->tm_id != representor->port_id)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* set all the parameters to 0 first. */
+	memset(cap, 0, sizeof(*cap));
+
+	switch (tm_node->level) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		cap->shaper_private_supported = 1;
+		cap->shaper_private_dual_rate_supported = 0;
+		cap->shaper_private_rate_min = 1;
+		cap->shaper_private_rate_max = UINT32_MAX;
+		cap->shaper_shared_n_max = 0;
+
+		cap->nonleaf.sched_n_children_max = IPN3KE_TM_VT_NODE_NUM;
+		cap->nonleaf.sched_sp_n_priorities_max = 1;
+		cap->nonleaf.sched_wfq_n_children_per_group_max =
+			IPN3KE_TM_VT_NODE_NUM;
+		cap->nonleaf.sched_wfq_n_groups_max = 1;
+		cap->nonleaf.sched_wfq_weight_max = 1;
+
+		cap->stats_mask = STATS_MASK_DEFAULT;
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		cap->shaper_private_supported = 1;
+		cap->shaper_private_dual_rate_supported = 0;
+		cap->shaper_private_rate_min = 1;
+		cap->shaper_private_rate_max = UINT32_MAX;
+		cap->shaper_shared_n_max = 0;
+
+		cap->nonleaf.sched_n_children_max = IPN3KE_TM_COS_NODE_NUM;
+		cap->nonleaf.sched_sp_n_priorities_max = 1;
+		cap->nonleaf.sched_wfq_n_children_per_group_max =
+			IPN3KE_TM_COS_NODE_NUM;
+		cap->nonleaf.sched_wfq_n_groups_max = 1;
+		cap->nonleaf.sched_wfq_weight_max = 1;
+
+		cap->stats_mask = STATS_MASK_DEFAULT;
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		cap->shaper_private_supported = 0;
+		cap->shaper_private_dual_rate_supported = 0;
+		cap->shaper_private_rate_min = 0;
+		cap->shaper_private_rate_max = 0;
+		cap->shaper_shared_n_max = 0;
+
+		cap->leaf.cman_head_drop_supported = 0;
+		cap->leaf.cman_wred_packet_mode_supported = WRED_SUPPORTED;
+		cap->leaf.cman_wred_byte_mode_supported = 0;
+		cap->leaf.cman_wred_context_private_supported = WRED_SUPPORTED;
+		cap->leaf.cman_wred_context_shared_n_max = 0;
+
+		cap->stats_mask = STATS_MASK_QUEUE;
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int
+ipn3ke_tm_shaper_parame_trans(struct rte_tm_shaper_params *profile,
+	struct ipn3ke_tm_shaper_profile *local_profile,
+	const struct ipn3ke_tm_shaper_params_range_type *ref_data)
+{
+	int i;
+	const struct ipn3ke_tm_shaper_params_range_type *r;
+	uint64_t rate;
+
+	rate = profile->peak.rate;
+	for (i = 0, r = ref_data; i < IPN3KE_TM_SHAPER_RANGE_NUM; i++, r++) {
+		if ((rate >= r->low) &&
+		(rate <= r->high)) {
+			local_profile->m = (rate / 4) / r->exp2;
+			local_profile->e = r->exp;
+			local_profile->rate = rate;
+
+			return 0;
+		}
+	}
+
+	return -1;
+}
+static int
+ipn3ke_tm_shaper_profile_add(struct rte_eth_dev *dev,
+	uint32_t shaper_profile_id,
+	struct rte_tm_shaper_params *profile,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	struct ipn3ke_tm_shaper_profile *sp;
+
+	/* Shaper profile must not exist. */
+	sp = ipn3ke_hw_tm_shaper_profile_search(hw, shaper_profile_id, error);
+	if (!sp || (sp && sp->valid))
+		return -rte_tm_error_set(error,
+					EEXIST,
+					RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+					NULL,
+					rte_strerror(EEXIST));
+
+	/* Profile must not be NULL. */
+	if (profile == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_SHAPER_PROFILE,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* Peak rate: non-zero, 32-bit */
+	if (profile->peak.rate == 0 ||
+		profile->peak.rate >= IPN3KE_TM_SHAPER_PEAK_RATE_MAX)
+		return -rte_tm_error_set(error,
+				EINVAL,
+				RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_RATE,
+				NULL,
+				rte_strerror(EINVAL));
+
+	/* Peak size: non-zero, 32-bit */
+	if (profile->peak.size != 0)
+		return -rte_tm_error_set(error,
+				EINVAL,
+				RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE,
+				NULL,
+				rte_strerror(EINVAL));
+
+	/* Dual-rate profiles are not supported. */
+	if (profile->committed.rate >= IPN3KE_TM_SHAPER_COMMITTED_RATE_MAX)
+		return -rte_tm_error_set(error,
+				EINVAL,
+				RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_RATE,
+				NULL,
+				rte_strerror(EINVAL));
+
+	/* Packet length adjust: 24 bytes */
+	if (profile->pkt_length_adjust != 0)
+		return -rte_tm_error_set(error,
+				EINVAL,
+				RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN,
+				NULL,
+				rte_strerror(EINVAL));
+
+	if (ipn3ke_tm_shaper_parame_trans(profile,
+					sp,
+					ipn3ke_tm_shaper_params_rang)) {
+		return -rte_tm_error_set(error,
+				EINVAL,
+				RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_RATE,
+				NULL,
+				rte_strerror(EINVAL));
+	} else {
+		sp->valid = 1;
+		rte_memcpy(&sp->params, profile, sizeof(sp->params));
+	}
+
+	tm->h.n_shaper_profiles++;
+
+	return 0;
+}
+
+/* Traffic manager shaper profile delete */
+static int
+ipn3ke_tm_shaper_profile_delete(struct rte_eth_dev *dev,
+	uint32_t shaper_profile_id,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	struct ipn3ke_tm_shaper_profile *sp;
+
+	/* Check existing */
+	sp = ipn3ke_hw_tm_shaper_profile_search(hw, shaper_profile_id, error);
+	if (!sp || (sp && !sp->valid))
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	sp->valid = 0;
+	tm->h.n_shaper_profiles--;
+
+	return 0;
+}
+
+static int
+ipn3ke_tm_tdrop_profile_check(struct rte_eth_dev *dev,
+	uint32_t tdrop_profile_id,
+	struct rte_tm_wred_params *profile,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_tdrop_profile *tp;
+	enum rte_tm_color color;
+
+	/* TDROP profile ID must not be NONE. */
+	if (tdrop_profile_id == RTE_TM_WRED_PROFILE_ID_NONE)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_WRED_PROFILE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* TDROP profile must not exist. */
+	tp = ipn3ke_hw_tm_tdrop_profile_search(hw, tdrop_profile_id);
+
+	/* Profile must not be NULL. */
+	if (profile == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_WRED_PROFILE,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* TDROP profile should be in packet mode */
+	if (profile->packet_mode != 0)
+		return -rte_tm_error_set(error,
+					ENOTSUP,
+					RTE_TM_ERROR_TYPE_WRED_PROFILE,
+					NULL,
+					rte_strerror(ENOTSUP));
+
+	/* min_th <= max_th, max_th > 0  */
+	for (color = RTE_TM_GREEN; color <= RTE_TM_GREEN; color++) {
+		uint64_t min_th = profile->red_params[color].min_th;
+		uint64_t max_th = profile->red_params[color].max_th;
+		uint32_t th1, th2;
+
+		th1 = (uint32_t)(min_th & IPN3KE_TDROP_TH1_MASK);
+		th2 = (uint32_t)((min_th >> IPN3KE_TDROP_TH1_SHIFT) &
+				IPN3KE_TDROP_TH2_MASK);
+		if (((min_th >> IPN3KE_TDROP_TH1_SHIFT) >>
+				IPN3KE_TDROP_TH1_SHIFT) ||
+			max_th != 0)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_WRED_PROFILE,
+						NULL,
+						rte_strerror(EINVAL));
+	}
+
+	return 0;
+}
+
+static int
+ipn3ke_hw_tm_tdrop_wr(struct ipn3ke_hw *hw,
+				struct ipn3ke_tm_tdrop_profile *tp)
+{
+	if (tp->valid) {
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_CCB_PROFILE_MS,
+				0,
+				tp->th2,
+				IPN3KE_CCB_PROFILE_MS_MASK);
+
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_CCB_PROFILE_P,
+				tp->tdrop_profile_id,
+				tp->th1,
+				IPN3KE_CCB_PROFILE_MASK);
+	} else {
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_CCB_PROFILE_MS,
+				0,
+				0,
+				IPN3KE_CCB_PROFILE_MS_MASK);
+
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_CCB_PROFILE_P,
+				tp->tdrop_profile_id,
+				0,
+				IPN3KE_CCB_PROFILE_MASK);
+	}
+
+	return 0;
+}
+
+/* Traffic manager TDROP profile add */
+static int
+ipn3ke_tm_tdrop_profile_add(struct rte_eth_dev *dev,
+	uint32_t tdrop_profile_id,
+	struct rte_tm_wred_params *profile,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	struct ipn3ke_tm_tdrop_profile *tp;
+	int status;
+	uint64_t min_th;
+	uint32_t th1, th2;
+
+	/* Check input params */
+	status = ipn3ke_tm_tdrop_profile_check(dev,
+					tdrop_profile_id,
+					profile,
+					error);
+	if (status)
+		return status;
+
+	/* Memory allocation */
+	tp = &hw->tdrop_profile[tdrop_profile_id];
+
+	/* Fill in */
+	tp->valid = 1;
+	min_th = profile->red_params[RTE_TM_GREEN].min_th;
+	th1 = (uint32_t)(min_th & IPN3KE_TDROP_TH1_MASK);
+	th2 = (uint32_t)((min_th >> IPN3KE_TDROP_TH1_SHIFT) &
+			IPN3KE_TDROP_TH2_MASK);
+	tp->th1 = th1;
+	tp->th2 = th2;
+	rte_memcpy(&tp->params, profile, sizeof(tp->params));
+
+	/* Add to list */
+	tm->h.n_tdrop_profiles++;
+
+	/* Write FPGA */
+	ipn3ke_hw_tm_tdrop_wr(hw, tp);
+
+	return 0;
+}
+
+/* Traffic manager TDROP profile delete */
+static int
+ipn3ke_tm_tdrop_profile_delete(struct rte_eth_dev *dev,
+	uint32_t tdrop_profile_id,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	struct ipn3ke_tm_tdrop_profile *tp;
+
+	/* Check existing */
+	tp = ipn3ke_hw_tm_tdrop_profile_search(hw, tdrop_profile_id);
+	if (tp == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_WRED_PROFILE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* Check unused */
+	if (tp->n_users)
+		return -rte_tm_error_set(error,
+					EBUSY,
+					RTE_TM_ERROR_TYPE_WRED_PROFILE_ID,
+					NULL,
+					rte_strerror(EBUSY));
+
+	/* Set free */
+	tp->valid = 0;
+	tm->h.n_tdrop_profiles--;
+
+	/* Write FPGA */
+	ipn3ke_hw_tm_tdrop_wr(hw, tp);
+
+	return 0;
+}
+
+static int
+ipn3ke_tm_node_add_check_parameter(uint32_t tm_id,
+	uint32_t node_id,
+	uint32_t parent_node_id,
+	uint32_t priority,
+	uint32_t weight,
+	uint32_t level_id,
+	struct rte_tm_node_params *params,
+	struct rte_tm_error *error)
+{
+	uint32_t level_of_node_id;
+	uint32_t node_index;
+	uint32_t parent_level_id;
+
+	if (node_id == RTE_TM_NODE_ID_NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* priority: must be 0, 1, 2, 3 */
+	if (priority > IPN3KE_TM_NODE_PRIORITY_HIGHEST)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PRIORITY,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* weight: must be 1 .. 255 */
+	if (weight > IPN3KE_TM_NODE_WEIGHT_MAX)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_WEIGHT,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* check node id and parent id*/
+	level_of_node_id = node_id / IPN3KE_TM_NODE_LEVEL_MOD;
+	if (level_of_node_id != level_id)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+	node_index = node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+	parent_level_id = parent_node_id / IPN3KE_TM_NODE_LEVEL_MOD;
+	switch (level_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		if (node_index != tm_id)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+		if (parent_node_id != RTE_TM_NODE_ID_NULL)
+			return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		if (node_index >= IPN3KE_TM_VT_NODE_NUM)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+		if (parent_level_id != IPN3KE_TM_NODE_LEVEL_PORT)
+			return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		if (node_index >= IPN3KE_TM_COS_NODE_NUM)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+		if (parent_level_id != IPN3KE_TM_NODE_LEVEL_VT)
+			return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+		break;
+	default:
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_LEVEL_ID,
+					NULL,
+					rte_strerror(EINVAL));
+	}
+
+	/* params: must not be NULL */
+	if (params == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARAMS,
+					NULL,
+					rte_strerror(EINVAL));
+	/* No shared shapers */
+	if (params->n_shared_shapers != 0)
+		return -rte_tm_error_set(error,
+				EINVAL,
+				RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_SHAPERS,
+				NULL,
+				rte_strerror(EINVAL));
+	return 0;
+}
+static int
+ipn3ke_tm_node_add_check_mount(uint32_t tm_id,
+	uint32_t node_id,
+	uint32_t parent_node_id,
+	uint32_t level_id,
+	struct rte_tm_error *error)
+{
+	/*struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);*/
+	uint32_t node_index;
+	uint32_t parent_index;
+	uint32_t parent_index1;
+
+	node_index = node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+	parent_index = parent_node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+	parent_index1 = node_index / IPN3KE_TM_NODE_MOUNT_MAX;
+	switch (level_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		if (parent_index != tm_id)
+			return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		if (parent_index != parent_index1)
+			return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+		break;
+	default:
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_LEVEL_ID,
+					NULL,
+					rte_strerror(EINVAL));
+	}
+
+	return 0;
+}
+
+/* Traffic manager node add */
+static int
+ipn3ke_tm_node_add(struct rte_eth_dev *dev,
+	uint32_t node_id,
+	uint32_t parent_node_id,
+	uint32_t priority,
+	uint32_t weight,
+	uint32_t level_id,
+	struct rte_tm_node_params *params,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	uint32_t tm_id;
+	struct ipn3ke_tm_node *n, *parent_node;
+	uint32_t node_state, state_mask;
+	uint32_t node_index;
+	uint32_t parent_index;
+	int status;
+
+	/* Checks */
+	if (tm->hierarchy_frozen)
+		return -rte_tm_error_set(error,
+					EBUSY,
+					RTE_TM_ERROR_TYPE_UNSPECIFIED,
+					NULL,
+					rte_strerror(EBUSY));
+
+	tm_id = tm->tm_id;
+
+	status = ipn3ke_tm_node_add_check_parameter(tm_id,
+						node_id,
+						parent_node_id,
+						priority,
+						weight,
+						level_id,
+						params,
+						error);
+	if (status)
+		return status;
+
+	status = ipn3ke_tm_node_add_check_mount(tm_id,
+						node_id,
+						parent_node_id,
+						level_id,
+						error);
+	if (status)
+		return status;
+
+	/* Shaper profile ID must not be NONE. */
+	if ((params->shaper_profile_id != RTE_TM_SHAPER_PROFILE_ID_NONE) &&
+		(params->shaper_profile_id != node_id))
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* Memory allocation */
+	state_mask = 0;
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_IDLE);
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_CONFIGURED_DEL);
+	n = ipn3ke_hw_tm_node_search(hw, tm_id, node_id, state_mask);
+	if (!n)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_UNSPECIFIED,
+					NULL,
+					rte_strerror(EINVAL));
+	node_state = n->node_state;
+
+	/* Check parent node */
+	state_mask = 0;
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_CONFIGURED_ADD);
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_COMMITTED);
+	if (parent_node_id != RTE_TM_NODE_ID_NULL) {
+		parent_node = ipn3ke_hw_tm_node_search(hw,
+							tm_id,
+							parent_node_id,
+							state_mask);
+		if (!parent_node)
+			return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+	} else
+		parent_node = NULL;
+
+	node_index = node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+	parent_index = parent_node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+	switch (level_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		n->node_state = IPN3KE_TM_NODE_STATE_CONFIGURED_ADD;
+		n->tm_id = tm_id;
+		tm->h.port_commit_node = n;
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		if (node_state == IPN3KE_TM_NODE_STATE_IDLE) {
+			TAILQ_INSERT_TAIL(&tm->h.vt_commit_node_list, n, node);
+			if (parent_node)
+				parent_node->n_children++;
+			tm->h.n_vt_nodes++;
+		} else if (node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_DEL) {
+			if (parent_node)
+				parent_node->n_children++;
+			tm->h.n_vt_nodes++;
+		}
+		n->node_state = IPN3KE_TM_NODE_STATE_CONFIGURED_ADD;
+		n->parent_node_id = parent_node_id;
+		n->tm_id = tm_id;
+		n->parent_node = parent_node;
+
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		if (node_state == IPN3KE_TM_NODE_STATE_IDLE) {
+			TAILQ_INSERT_TAIL(&tm->h.cos_commit_node_list,
+				n, node);
+			if (parent_node)
+				parent_node->n_children++;
+			tm->h.n_cos_nodes++;
+		} else if (node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_DEL) {
+			if (parent_node)
+				parent_node->n_children++;
+			tm->h.n_cos_nodes++;
+		}
+		n->node_state = IPN3KE_TM_NODE_STATE_CONFIGURED_ADD;
+		n->parent_node_id = parent_node_id;
+		n->tm_id = tm_id;
+		n->parent_node = parent_node;
+
+		break;
+	default:
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_LEVEL_ID,
+					NULL,
+					rte_strerror(EINVAL));
+	}
+
+	/* Fill in */
+	n->priority = priority;
+	n->weight = weight;
+
+	if (n->level == IPN3KE_TM_NODE_LEVEL_COS &&
+		params->leaf.cman == RTE_TM_CMAN_TAIL_DROP)
+		n->tdrop_profile = ipn3ke_hw_tm_tdrop_profile_search(hw,
+			params->leaf.wred.wred_profile_id);
+
+	rte_memcpy(&n->params, params, sizeof(n->params));
+
+	return 0;
+}
+
+static int
+ipn3ke_tm_node_del_check_parameter(uint32_t tm_id,
+	uint32_t node_id,
+	struct rte_tm_error *error)
+{
+	uint32_t level_of_node_id;
+	uint32_t node_index;
+
+	if (node_id == RTE_TM_NODE_ID_NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	/* check node id and parent id*/
+	level_of_node_id = node_id / IPN3KE_TM_NODE_LEVEL_MOD;
+	node_index = node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+	switch (level_of_node_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		if (node_index != tm_id)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		if (node_index >= IPN3KE_TM_VT_NODE_NUM)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		if (node_index >= IPN3KE_TM_COS_NODE_NUM)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+		break;
+	default:
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_LEVEL_ID,
+					NULL,
+					rte_strerror(EINVAL));
+	}
+
+	return 0;
+}
+
+/* Traffic manager node delete */
+static int
+ipn3ke_pmd_tm_node_delete(struct rte_eth_dev *dev,
+	uint32_t node_id,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	struct ipn3ke_tm_node *n, *parent_node;
+	uint32_t tm_id;
+	int status;
+	uint32_t level_of_node_id;
+	uint32_t node_index;
+	uint32_t node_state;
+	uint32_t state_mask;
+
+	/* Check hierarchy changes are currently allowed */
+	if (tm->hierarchy_frozen)
+		return -rte_tm_error_set(error,
+					EBUSY,
+					RTE_TM_ERROR_TYPE_UNSPECIFIED,
+					NULL,
+					rte_strerror(EBUSY));
+
+	tm_id = tm->tm_id;
+
+	status = ipn3ke_tm_node_del_check_parameter(tm_id,
+						node_id,
+						error);
+	if (status)
+		return status;
+
+	/* Check existing */
+	state_mask = 0;
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_CONFIGURED_ADD);
+	IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_COMMITTED);
+	n = ipn3ke_hw_tm_node_search(hw, tm_id, node_id, state_mask);
+	if (n == NULL)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	if (n->n_children > 0)
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+
+	node_state = n->node_state;
+
+	level_of_node_id = node_id / IPN3KE_TM_NODE_LEVEL_MOD;
+	node_index = node_id % IPN3KE_TM_NODE_LEVEL_MOD;
+
+	/* Check parent node */
+	if (n->parent_node_id != RTE_TM_NODE_ID_NULL) {
+		state_mask = 0;
+		IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_CONFIGURED_ADD);
+		IPN3KE_BIT_SET(state_mask, IPN3KE_TM_NODE_STATE_COMMITTED);
+		parent_node = ipn3ke_hw_tm_node_search(hw,
+						tm_id,
+						n->parent_node_id,
+						state_mask);
+		if (!parent_node)
+			return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
+					NULL,
+					rte_strerror(EINVAL));
+		if (n->parent_node != parent_node)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+	} else
+		parent_node = NULL;
+
+	switch (level_of_node_id) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		if (tm->h.port_node != n)
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_NODE_ID,
+						NULL,
+						rte_strerror(EINVAL));
+		n->node_state = IPN3KE_TM_NODE_STATE_CONFIGURED_DEL;
+		tm->h.port_commit_node = n;
+
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		if (node_state == IPN3KE_TM_NODE_STATE_COMMITTED) {
+			if (parent_node)
+				TAILQ_REMOVE(&parent_node->children_node_list,
+					n, node);
+			TAILQ_INSERT_TAIL(&tm->h.vt_commit_node_list, n, node);
+			if (parent_node)
+				parent_node->n_children--;
+			tm->h.n_vt_nodes--;
+		} else if (node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_ADD) {
+			if (parent_node)
+				parent_node->n_children--;
+			tm->h.n_vt_nodes--;
+		}
+		n->node_state = IPN3KE_TM_NODE_STATE_CONFIGURED_DEL;
+
+		break;
+
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		if (node_state == IPN3KE_TM_NODE_STATE_COMMITTED) {
+			if (parent_node)
+				TAILQ_REMOVE(&parent_node->children_node_list,
+					n, node);
+			TAILQ_INSERT_TAIL(&tm->h.cos_commit_node_list,
+				n, node);
+			if (parent_node)
+				parent_node->n_children--;
+			tm->h.n_cos_nodes--;
+		} else if (node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_ADD) {
+			if (parent_node)
+				parent_node->n_children--;
+			tm->h.n_cos_nodes--;
+		}
+		n->node_state = IPN3KE_TM_NODE_STATE_CONFIGURED_DEL;
+
+		break;
+	default:
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_LEVEL_ID,
+					NULL,
+					rte_strerror(EINVAL));
+	}
+
+	return 0;
+}
+static int
+ipn3ke_tm_hierarchy_commit_check(struct rte_eth_dev *dev,
+						struct rte_tm_error *error)
+{
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	uint32_t tm_id;
+	struct ipn3ke_tm_node_list *nl;
+	struct ipn3ke_tm_node *n, *parent_node;
+	enum ipn3ke_tm_node_state node_state;
+
+	tm_id = tm->tm_id;
+
+	nl = &tm->h.cos_commit_node_list;
+	TAILQ_FOREACH(n, nl, node) {
+		node_state = n->node_state;
+		parent_node = n->parent_node;
+		if (n->node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_ADD) {
+			if ((n->parent_node_id == RTE_TM_NODE_ID_NULL) ||
+				(n->level != IPN3KE_TM_NODE_LEVEL_COS) ||
+				(n->tm_id != tm_id) ||
+				(parent_node == NULL) ||
+				(parent_node &&
+					(parent_node->node_state ==
+					IPN3KE_TM_NODE_STATE_CONFIGURED_DEL)) ||
+				(parent_node &&
+					(parent_node->node_state ==
+						IPN3KE_TM_NODE_STATE_IDLE)) ||
+				(n->shaper_profile.valid == 0))
+				return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+		} else if (n->node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_DEL)
+			if ((n->level != IPN3KE_TM_NODE_LEVEL_COS) ||
+				(n->n_children != 0))
+				return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+		else
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+	}
+
+	nl = &tm->h.vt_commit_node_list;
+	TAILQ_FOREACH(n, nl, node) {
+		node_state = n->node_state;
+		parent_node = n->parent_node;
+		if (n->node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_ADD) {
+			if ((n->parent_node_id == RTE_TM_NODE_ID_NULL) ||
+				(n->level != IPN3KE_TM_NODE_LEVEL_VT) ||
+				(n->tm_id != tm_id) ||
+				(parent_node == NULL) ||
+				(parent_node &&
+					(parent_node->node_state ==
+					IPN3KE_TM_NODE_STATE_CONFIGURED_DEL)) ||
+				(parent_node &&
+					(parent_node->node_state ==
+						IPN3KE_TM_NODE_STATE_IDLE)) ||
+				(n->shaper_profile.valid == 0))
+				return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+		} else if (n->node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_DEL)
+			if ((n->level != IPN3KE_TM_NODE_LEVEL_VT) ||
+				(n->n_children != 0))
+				return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+		else
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+	}
+
+	n = tm->h.port_commit_node;
+	if (n &&
+		((n->parent_node_id != RTE_TM_NODE_ID_NULL) ||
+		(n->level != IPN3KE_TM_NODE_LEVEL_PORT) ||
+		(n->tm_id != tm_id) ||
+		(n->parent_node != NULL) ||
+		(n->shaper_profile.valid == 0)))
+		return -rte_tm_error_set(error,
+					EINVAL,
+					RTE_TM_ERROR_TYPE_UNSPECIFIED,
+					NULL,
+					rte_strerror(EINVAL));
+
+	return 0;
+}
+static int
+ipn3ke_hw_tm_node_wr(struct ipn3ke_hw *hw,
+				struct ipn3ke_tm_node *n)
+{
+	uint32_t level;
+	uint32_t node_index;
+
+	level = n->level;
+	node_index = n->node_index;
+
+	switch (level) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		/**
+		 * Configure Type
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_TYPE_L3_X,
+				n->node_index,
+				n->priority,
+				IPN3KE_QOS_TYPE_MASK);
+
+		/**
+		 * Configure Sch_wt
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_SCH_WT_L3_X,
+				n->node_index,
+				n->weight,
+				IPN3KE_QOS_SCH_WT_MASK);
+
+		/**
+		 * Configure Shap_wt
+		 */
+		if (n->shaper_profile.valid)
+			IPN3KE_MASK_WRITE_REG(hw,
+					IPN3KE_QOS_SHAP_WT_L3_X,
+					n->node_index,
+					((n->shaper_profile.e << 10) |
+						n->shaper_profile.m),
+					IPN3KE_QOS_SHAP_WT_MASK);
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		/**
+		 * Configure Type
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_TYPE_L2_X,
+				n->node_index,
+				n->priority,
+				IPN3KE_QOS_TYPE_MASK);
+
+		/**
+		 * Configure Sch_wt
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_SCH_WT_L2_X,
+				n->node_index,
+				n->weight,
+				IPN3KE_QOS_SCH_WT_MASK);
+
+		/**
+		 * Configure Shap_wt
+		 */
+		if (n->shaper_profile.valid)
+			IPN3KE_MASK_WRITE_REG(hw,
+					IPN3KE_QOS_SHAP_WT_L2_X,
+					n->node_index,
+					((n->shaper_profile.e << 10) |
+						n->shaper_profile.m),
+					IPN3KE_QOS_SHAP_WT_MASK);
+
+		/**
+		 * Configure Map
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_MAP_L2_X,
+				n->node_index,
+				n->parent_node->node_index,
+				IPN3KE_QOS_MAP_L2_MASK);
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		/**
+		 * Configure Tail Drop mapping
+		 */
+		if (n->tdrop_profile && n->tdrop_profile->valid) {
+			IPN3KE_MASK_WRITE_REG(hw,
+					IPN3KE_CCB_QPROFILE_Q,
+					n->node_index,
+					n->tdrop_profile->tdrop_profile_id,
+					IPN3KE_CCB_QPROFILE_MASK);
+		}
+
+		/**
+		 * Configure Type
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_TYPE_L1_X,
+				n->node_index,
+				n->priority,
+				IPN3KE_QOS_TYPE_MASK);
+
+		/**
+		 * Configure Sch_wt
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_SCH_WT_L1_X,
+				n->node_index,
+				n->weight,
+				IPN3KE_QOS_SCH_WT_MASK);
+
+		/**
+		 * Configure Shap_wt
+		 */
+		if (n->shaper_profile.valid)
+			IPN3KE_MASK_WRITE_REG(hw,
+					IPN3KE_QOS_SHAP_WT_L1_X,
+					n->node_index,
+					((n->shaper_profile.e << 10) |
+						n->shaper_profile.m),
+					IPN3KE_QOS_SHAP_WT_MASK);
+
+		/**
+		 * Configure COS queue to port
+		 */
+		while (IPN3KE_MASK_READ_REG(hw,
+					IPN3KE_QM_UID_CONFIG_CTRL,
+					0,
+					0x80000000))
+			;
+
+		IPN3KE_MASK_WRITE_REG(hw,
+			IPN3KE_QM_UID_CONFIG_DATA,
+			0,
+			(1 << 8 | n->parent_node->parent_node->node_index),
+			0x1FF);
+
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QM_UID_CONFIG_CTRL,
+				0,
+				n->node_index,
+				0xFFFFF);
+
+		while (IPN3KE_MASK_READ_REG(hw,
+					IPN3KE_QM_UID_CONFIG_CTRL,
+					0,
+					0x80000000))
+			;
+
+		/**
+		 * Configure Map
+		 */
+		IPN3KE_MASK_WRITE_REG(hw,
+				IPN3KE_QOS_MAP_L1_X,
+				n->node_index,
+				n->parent_node->node_index,
+				IPN3KE_QOS_MAP_L1_MASK);
+
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+static int
+ipn3ke_tm_hierarchy_hw_commit(struct rte_eth_dev *dev,
+					struct rte_tm_error *error)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	struct ipn3ke_tm_node_list *nl;
+	struct ipn3ke_tm_node *n, *nn, *parent_node;
+
+	n = tm->h.port_commit_node;
+	if (n) {
+		if (n->node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_ADD) {
+			tm->h.port_commit_node = NULL;
+
+			n->node_state = IPN3KE_TM_NODE_STATE_COMMITTED;
+		} else if (n->node_state ==
+					IPN3KE_TM_NODE_STATE_CONFIGURED_DEL) {
+			tm->h.port_commit_node = NULL;
+
+			n->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+			n->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+			n->weight = 0;
+			n->tm_id = RTE_TM_NODE_ID_NULL;
+		} else
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+		ipn3ke_hw_tm_node_wr(hw, n);
+	}
+
+	nl = &tm->h.vt_commit_node_list;
+	for (n = TAILQ_FIRST(nl); n; nn) {
+		nn = TAILQ_NEXT(n, node);
+		if (n->node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_ADD) {
+			n->node_state = IPN3KE_TM_NODE_STATE_COMMITTED;
+			parent_node = n->parent_node;
+			TAILQ_REMOVE(nl, n, node);
+			TAILQ_INSERT_TAIL(&parent_node->children_node_list,
+						n, node);
+		} else if (n->node_state ==
+					IPN3KE_TM_NODE_STATE_CONFIGURED_DEL) {
+			parent_node = n->parent_node;
+			TAILQ_REMOVE(nl, n, node);
+
+			n->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+			n->parent_node_id = RTE_TM_NODE_ID_NULL;
+			n->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+			n->weight = 0;
+			n->tm_id = RTE_TM_NODE_ID_NULL;
+			n->parent_node = NULL;
+		} else
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+		ipn3ke_hw_tm_node_wr(hw, n);
+		n = nn;
+	}
+
+	nl = &tm->h.cos_commit_node_list;
+	for (n = TAILQ_FIRST(nl); n; nn) {
+		nn = TAILQ_NEXT(n, node);
+		if (n->node_state == IPN3KE_TM_NODE_STATE_CONFIGURED_ADD) {
+			n->node_state = IPN3KE_TM_NODE_STATE_COMMITTED;
+			parent_node = n->parent_node;
+			TAILQ_REMOVE(nl, n, node);
+			TAILQ_INSERT_TAIL(&parent_node->children_node_list,
+					n, node);
+		} else if (n->node_state ==
+					IPN3KE_TM_NODE_STATE_CONFIGURED_DEL) {
+			n->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+			parent_node = n->parent_node;
+			TAILQ_REMOVE(nl, n, node);
+
+			n->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+			n->parent_node_id = RTE_TM_NODE_ID_NULL;
+			n->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+			n->weight = 0;
+			n->tm_id = RTE_TM_NODE_ID_NULL;
+			n->parent_node = NULL;
+
+			if (n->tdrop_profile)
+				n->tdrop_profile->n_users--;
+		} else
+			return -rte_tm_error_set(error,
+						EINVAL,
+						RTE_TM_ERROR_TYPE_UNSPECIFIED,
+						NULL,
+						rte_strerror(EINVAL));
+		ipn3ke_hw_tm_node_wr(hw, n);
+		n = nn;
+	}
+
+	return 0;
+}
+
+static int
+ipn3ke_tm_hierarchy_commit_clear(struct rte_eth_dev *dev)
+{
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	struct ipn3ke_tm_node_list *nl;
+	struct ipn3ke_tm_node *n;
+	struct ipn3ke_tm_node *nn;
+
+	n = tm->h.port_commit_node;
+	if (n) {
+		n->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+		n->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+		n->weight = 0;
+		n->tm_id = RTE_TM_NODE_ID_NULL;
+		n->n_children = 0;
+
+		tm->h.port_commit_node = NULL;
+	}
+
+	nl = &tm->h.vt_commit_node_list;
+	for (n = TAILQ_FIRST(nl); n; nn) {
+		nn = TAILQ_NEXT(n, node);
+
+		n->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+		n->parent_node_id = RTE_TM_NODE_ID_NULL;
+		n->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+		n->weight = 0;
+		n->tm_id = RTE_TM_NODE_ID_NULL;
+		n->parent_node = NULL;
+		n->n_children = 0;
+		tm->h.n_vt_nodes--;
+
+		TAILQ_REMOVE(nl, n, node);
+		n = nn;
+	}
+
+	nl = &tm->h.cos_commit_node_list;
+	for (n = TAILQ_FIRST(nl); n; nn) {
+		nn = TAILQ_NEXT(n, node);
+
+		n->node_state = IPN3KE_TM_NODE_STATE_IDLE;
+		n->parent_node_id = RTE_TM_NODE_ID_NULL;
+		n->priority = IPN3KE_TM_NODE_PRIORITY_NORMAL0;
+		n->weight = 0;
+		n->tm_id = RTE_TM_NODE_ID_NULL;
+		n->parent_node = NULL;
+		tm->h.n_cos_nodes--;
+
+		TAILQ_REMOVE(nl, n, node);
+		n = nn;
+	}
+
+	return 0;
+}
+
+static void
+ipn3ke_tm_show(struct rte_eth_dev *dev)
+{
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	uint32_t tm_id;
+	struct ipn3ke_tm_node_list *vt_nl, *cos_nl;
+	struct ipn3ke_tm_node *port_n, *vt_n, *cos_n;
+	char *str_state[IPN3KE_TM_NODE_STATE_MAX] = {"Idle",
+						"CfgAdd",
+						"CfgDel",
+						"Committed"};
+
+	tm_id = tm->tm_id;
+
+	printf("*************HQoS Tree(%d)*************\n", tm_id);
+
+	port_n = tm->h.port_node;
+	printf("Port: (%d|%s)\n", port_n->node_index,
+				str_state[port_n->node_state]);
+
+	vt_nl = &tm->h.port_node->children_node_list;
+	TAILQ_FOREACH(vt_n, vt_nl, node) {
+		cos_nl = &vt_n->children_node_list;
+		printf("    VT%d: ", vt_n->node_index);
+		TAILQ_FOREACH(cos_n, cos_nl, node) {
+			if (cos_n->parent_node_id !=
+				(vt_n->node_index + IPN3KE_TM_NODE_LEVEL_MOD))
+				IPN3KE_ASSERT(0);
+			printf("(%d|%s), ", cos_n->node_index,
+					str_state[cos_n->node_state]);
+		}
+		printf("\n");
+	}
+}
+static void
+ipn3ke_tm_show_commmit(struct rte_eth_dev *dev)
+{
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	uint32_t tm_id;
+	struct ipn3ke_tm_node_list *nl;
+	struct ipn3ke_tm_node *n;
+	char *str_state[IPN3KE_TM_NODE_STATE_MAX] = {"Idle",
+						"CfgAdd",
+						"CfgDel",
+						"Committed"};
+
+	tm_id = tm->tm_id;
+
+	printf("*************Commit Tree(%d)*************\n", tm_id);
+	n = tm->h.port_commit_node;
+	printf("Port: ");
+	if (n)
+		printf("(%d|%s)", n->node_index, str_state[n->node_state]);
+	printf("\n");
+
+	nl = &tm->h.vt_commit_node_list;
+	printf("VT  : ");
+	TAILQ_FOREACH(n, nl, node) {
+		printf("(%d|%s), ", n->node_index, str_state[n->node_state]);
+	}
+	printf("\n");
+
+	nl = &tm->h.cos_commit_node_list;
+	printf("COS : ");
+	TAILQ_FOREACH(n, nl, node) {
+		printf("(%d|%s), ", n->node_index, str_state[n->node_state]);
+	}
+	printf("\n");
+}
+
+/* Traffic manager hierarchy commit */
+static int
+ipn3ke_tm_hierarchy_commit(struct rte_eth_dev *dev,
+	int clear_on_fail,
+	struct rte_tm_error *error)
+{
+	struct ipn3ke_tm_internals *tm = IPN3KE_DEV_PRIVATE_TO_TM(dev);
+	int status;
+
+	/* Checks */
+	if (tm->hierarchy_frozen)
+		return -rte_tm_error_set(error,
+					EBUSY,
+					RTE_TM_ERROR_TYPE_UNSPECIFIED,
+					NULL,
+					rte_strerror(EBUSY));
+
+	ipn3ke_tm_show_commmit(dev);
+
+	status = ipn3ke_tm_hierarchy_commit_check(dev, error);
+	if (status) {
+		if (clear_on_fail)
+			ipn3ke_tm_hierarchy_commit_clear(dev);
+		return status;
+	}
+
+	ipn3ke_tm_hierarchy_hw_commit(dev, error);
+	ipn3ke_tm_show(dev);
+
+	return 0;
+}
+
+const struct rte_tm_ops ipn3ke_tm_ops = {
+	.node_type_get = ipn3ke_pmd_tm_node_type_get,
+	.capabilities_get = ipn3ke_tm_capabilities_get,
+	.level_capabilities_get = ipn3ke_tm_level_capabilities_get,
+	.node_capabilities_get = ipn3ke_tm_node_capabilities_get,
+
+	.wred_profile_add = ipn3ke_tm_tdrop_profile_add,
+	.wred_profile_delete = ipn3ke_tm_tdrop_profile_delete,
+	.shared_wred_context_add_update = NULL,
+	.shared_wred_context_delete = NULL,
+
+	.shaper_profile_add = ipn3ke_tm_shaper_profile_add,
+	.shaper_profile_delete = ipn3ke_tm_shaper_profile_delete,
+	.shared_shaper_add_update = NULL,
+	.shared_shaper_delete = NULL,
+
+	.node_add = ipn3ke_tm_node_add,
+	.node_delete = ipn3ke_pmd_tm_node_delete,
+	.node_suspend = NULL,
+	.node_resume = NULL,
+	.hierarchy_commit = ipn3ke_tm_hierarchy_commit,
+
+	.node_parent_update = NULL,
+	.node_shaper_update = NULL,
+	.node_shared_shaper_update = NULL,
+	.node_stats_update = NULL,
+	.node_wfq_weight_mode_update = NULL,
+	.node_cman_update = NULL,
+	.node_wred_context_update = NULL,
+	.node_shared_wred_context_update = NULL,
+
+	.node_stats_read = NULL,
+};
+
+int
+ipn3ke_tm_ops_get(struct rte_eth_dev *ethdev,
+		void *arg)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(ethdev);
+	struct ipn3ke_rpst *rpst = IPN3KE_DEV_PRIVATE_TO_RPST(ethdev);
+	struct rte_tm_error error;
+
+	if (!arg)
+		return -EINVAL;
+
+	if (hw->acc_tm)
+		*(const void **)arg = &ipn3ke_tm_ops;
+	else if (rpst->i40e_pf_eth)
+		rte_tm_ops_get(rpst->i40e_pf_eth_port_id, &error);
+	else
+		return -EINVAL;
+
+	return 0;
+}
+
+int
+ipn3ke_hw_tm_hqos_node_dump(struct rte_eth_dev *dev,
+					uint32_t level,
+					uint32_t node_index,
+					int *parent,
+					uint32_t *type,
+					uint32_t *sch_wt,
+					uint32_t *shaper_m,
+					uint32_t *shaper_e,
+					uint32_t *ccb_profile_id,
+					uint32_t *th1,
+					uint32_t *th2)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+	uint32_t shaper;
+	uint32_t type_base, sch_wt_base, shap_wt_base;
+
+	switch (level) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		type_base    = IPN3KE_QOS_TYPE_L3_X;
+		sch_wt_base  = IPN3KE_QOS_SCH_WT_L3_X;
+		shap_wt_base = IPN3KE_QOS_SHAP_WT_L3_X;
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		type_base    = IPN3KE_QOS_TYPE_L2_X;
+		sch_wt_base  = IPN3KE_QOS_SCH_WT_L2_X;
+		shap_wt_base = IPN3KE_QOS_SHAP_WT_L2_X;
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		type_base    = IPN3KE_QOS_TYPE_L1_X;
+		sch_wt_base  = IPN3KE_QOS_SCH_WT_L1_X;
+		shap_wt_base = IPN3KE_QOS_SHAP_WT_L1_X;
+
+		break;
+	default:
+		return -1;
+	}
+
+	/**
+	 * Read Type
+	 */
+	(*type)	= IPN3KE_MASK_READ_REG(hw,
+				type_base,
+				node_index,
+				IPN3KE_QOS_TYPE_MASK);
+
+	/**
+	 * Read Sch_wt
+	 */
+	(*sch_wt) = IPN3KE_MASK_READ_REG(hw,
+					sch_wt_base,
+					node_index,
+					IPN3KE_QOS_SCH_WT_MASK);
+
+	/**
+	 * Read Shap_wt
+	 */
+	shaper = IPN3KE_MASK_READ_REG(hw,
+				shap_wt_base,
+				node_index,
+				IPN3KE_QOS_SHAP_WT_MASK);
+	(*shaper_m) = shaper & 0x3FF;
+	(*shaper_e) = (shaper >> 10) & 0xF;
+
+	/**
+	 * Read Parent and CCB Profile ID
+	 */
+	switch (level) {
+	case IPN3KE_TM_NODE_LEVEL_PORT:
+		(*parent) = -1;
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_VT:
+		(*parent) = IPN3KE_MASK_READ_REG(hw,
+						IPN3KE_QOS_MAP_L2_X,
+						node_index,
+						IPN3KE_QOS_MAP_L2_MASK);
+
+		break;
+	case IPN3KE_TM_NODE_LEVEL_COS:
+		(*parent) = IPN3KE_MASK_READ_REG(hw,
+						IPN3KE_QOS_MAP_L1_X,
+						node_index,
+						IPN3KE_QOS_MAP_L1_MASK);
+
+		(*ccb_profile_id) = IPN3KE_MASK_READ_REG(hw,
+						IPN3KE_CCB_QPROFILE_Q,
+						node_index,
+						IPN3KE_CCB_QPROFILE_MASK);
+		(*th1) = IPN3KE_MASK_READ_REG(hw,
+					IPN3KE_CCB_PROFILE_P,
+					(*ccb_profile_id),
+					IPN3KE_CCB_PROFILE_MASK);
+
+		(*th2) = IPN3KE_MASK_READ_REG(hw,
+					IPN3KE_CCB_PROFILE_MS,
+					0,
+					IPN3KE_CCB_PROFILE_MS_MASK);
+
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+int
+ipn3ke_hw_tm_ccb_node_dump(struct rte_eth_dev *dev,
+		uint32_t tdrop_profile_id,
+		uint32_t *th1,
+		uint32_t *th2)
+{
+	struct ipn3ke_hw *hw = IPN3KE_DEV_PRIVATE_TO_HW(dev);
+
+	(*th1) = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CCB_PROFILE_P,
+				tdrop_profile_id,
+				IPN3KE_CCB_PROFILE_MASK);
+
+	(*th2) = IPN3KE_MASK_READ_REG(hw,
+				IPN3KE_CCB_PROFILE_MS,
+				0,
+				IPN3KE_CCB_PROFILE_MS_MASK);
+
+	return 0;
+}
diff --git a/drivers/net/ipn3ke/ipn3ke_tm.h b/drivers/net/ipn3ke/ipn3ke_tm.h
new file mode 100644
index 0000000..43847d8
--- /dev/null
+++ b/drivers/net/ipn3ke/ipn3ke_tm.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+struct ipn3ke_rpst;
+
+#ifndef _IPN3KE_TM_H_
+#define _IPN3KE_TM_H_
+
+#include <rte_tm_driver.h>
+
+/* TM Levels */
+enum ipn3ke_tm_node_level {
+	IPN3KE_TM_NODE_LEVEL_PORT = 0,
+	IPN3KE_TM_NODE_LEVEL_VT,
+	IPN3KE_TM_NODE_LEVEL_COS,
+	IPN3KE_TM_NODE_LEVEL_MAX,
+};
+
+/* TM Shaper Profile */
+struct ipn3ke_tm_shaper_profile {
+	uint32_t valid;
+	uint32_t m;
+	uint32_t e;
+	uint64_t rate;
+	struct rte_tm_shaper_params params;
+};
+
+TAILQ_HEAD(ipn3ke_tm_shaper_profile_list, ipn3ke_tm_shaper_profile);
+
+
+#define IPN3KE_TDROP_TH1_MASK  0x1ffffff
+#define IPN3KE_TDROP_TH1_SHIFT (25)
+#define IPN3KE_TDROP_TH2_MASK  0x1ffffff
+
+/* TM TDROP Profile */
+struct ipn3ke_tm_tdrop_profile {
+	uint32_t tdrop_profile_id;
+	uint32_t th1;
+	uint32_t th2;
+	uint32_t n_users;
+	uint32_t valid;
+	struct rte_tm_wred_params params;
+};
+
+/* TM node priority */
+enum ipn3ke_tm_node_state {
+	IPN3KE_TM_NODE_STATE_IDLE = 0,
+	IPN3KE_TM_NODE_STATE_CONFIGURED_ADD,
+	IPN3KE_TM_NODE_STATE_CONFIGURED_DEL,
+	IPN3KE_TM_NODE_STATE_COMMITTED,
+	IPN3KE_TM_NODE_STATE_MAX,
+};
+
+TAILQ_HEAD(ipn3ke_tm_node_list, ipn3ke_tm_node);
+
+/* IPN3KE TM Node */
+struct ipn3ke_tm_node {
+	TAILQ_ENTRY(ipn3ke_tm_node) node;
+	uint32_t node_index;
+	uint32_t level;
+	uint32_t tm_id;
+	enum ipn3ke_tm_node_state node_state;
+	uint32_t parent_node_id;
+	uint32_t priority;
+	uint32_t weight;
+	struct ipn3ke_tm_node *parent_node;
+	struct ipn3ke_tm_shaper_profile shaper_profile;
+	struct ipn3ke_tm_tdrop_profile *tdrop_profile;
+	struct rte_tm_node_params params;
+	struct rte_tm_node_stats stats;
+	uint32_t n_children;
+	struct ipn3ke_tm_node_list children_node_list;
+};
+
+/* IPN3KE TM Hierarchy Specification */
+struct ipn3ke_tm_hierarchy {
+	struct ipn3ke_tm_node *port_node;
+	/*struct ipn3ke_tm_node_list vt_node_list;*/
+	/*struct ipn3ke_tm_node_list cos_node_list;*/
+
+	uint32_t n_shaper_profiles;
+	/*uint32_t n_shared_shapers;*/
+	uint32_t n_tdrop_profiles;
+	uint32_t n_vt_nodes;
+	uint32_t n_cos_nodes;
+
+	struct ipn3ke_tm_node *port_commit_node;
+	struct ipn3ke_tm_node_list vt_commit_node_list;
+	struct ipn3ke_tm_node_list cos_commit_node_list;
+
+	/*uint32_t n_tm_nodes[IPN3KE_TM_NODE_LEVEL_MAX];*/
+};
+
+struct ipn3ke_tm_internals {
+	/** Hierarchy specification
+	 *
+	 *     -Hierarchy is unfrozen at init and when port is stopped.
+	 *     -Hierarchy is frozen on successful hierarchy commit.
+	 *     -Run-time hierarchy changes are not allowed, therefore it makes
+	 *      sense to keep the hierarchy frozen after the port is started.
+	 */
+	struct ipn3ke_tm_hierarchy h;
+	int hierarchy_frozen;
+	int tm_started;
+	uint32_t tm_id;
+};
+
+#define IPN3KE_TM_COS_NODE_NUM      (64*1024)
+#define IPN3KE_TM_VT_NODE_NUM       (IPN3KE_TM_COS_NODE_NUM/8)
+#define IPN3KE_TM_10G_PORT_NODE_NUM (8)
+#define IPN3KE_TM_25G_PORT_NODE_NUM (4)
+
+#define IPN3KE_TM_NODE_LEVEL_MOD    (100000)
+#define IPN3KE_TM_NODE_MOUNT_MAX    (8)
+
+#define IPN3KE_TM_TDROP_PROFILE_NUM (2*1024)
+
+/* TM node priority */
+enum ipn3ke_tm_node_priority {
+	IPN3KE_TM_NODE_PRIORITY_NORMAL0 = 0,
+	IPN3KE_TM_NODE_PRIORITY_LOW,
+	IPN3KE_TM_NODE_PRIORITY_NORMAL1,
+	IPN3KE_TM_NODE_PRIORITY_HIGHEST,
+};
+
+#define IPN3KE_TM_NODE_WEIGHT_MAX UINT8_MAX
+
+void
+ipn3ke_tm_init(struct ipn3ke_rpst *rpst);
+int
+ipn3ke_tm_ops_get(struct rte_eth_dev *ethdev,
+		void *arg);
+
+#endif /* _IPN3KE_TM_H_ */
diff --git a/drivers/net/ipn3ke/meson.build b/drivers/net/ipn3ke/meson.build
new file mode 100644
index 0000000..e02ac25
--- /dev/null
+++ b/drivers/net/ipn3ke/meson.build
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Intel Corporation
+
+allow_experimental_apis = true
+sources += files('ipn3ke_ethdev.c',
+	'ipn3ke_representor.c',
+	'ipn3ke_tm.c',
+	'ipn3ke_flow.c')
+deps += ['kvargs', 'bus_pci', 'bus_ifpga']
diff --git a/drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map b/drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map
new file mode 100644
index 0000000..ef35398
--- /dev/null
+++ b/drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map
@@ -0,0 +1,4 @@
+DPDK_2.0 {
+
+	local: *;
+};
