From: Igor Romanov <igor.romanov@oktetlabs.ru>
EF100/Riverhead has different min limit. So, this limit should
be a part of NIC config, not define common for all NIC families.
Define maximum Tx descriptor number for Siena in the same way as
minimum for consistency.
Signed-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_impl.h | 1 +
drivers/net/sfc/base/efx.h | 5 +++++
drivers/net/sfc/base/efx_tx.c | 8 ++++----
drivers/net/sfc/base/hunt_nic.c | 1 +
drivers/net/sfc/base/medford2_nic.c | 1 +
drivers/net/sfc/base/medford_nic.c | 1 +
drivers/net/sfc/base/siena_impl.h | 3 +++
drivers/net/sfc/base/siena_nic.c | 3 ++-
8 files changed, 18 insertions(+), 5 deletions(-)
@@ -11,6 +11,7 @@
extern "C" {
#endif
+#define EF10_TXQ_MINNDESCS 512
/* Number of hardware PIO buffers (for compile-time resource dimensions) */
#define EF10_MAX_PIOBUF_NBUFS (16)
@@ -1272,6 +1272,7 @@ typedef struct efx_nic_cfg_s {
uint32_t enc_txq_limit;
uint32_t enc_rxq_limit;
uint32_t enc_txq_max_ndescs;
+ uint32_t enc_txq_min_ndescs;
uint32_t enc_buftbl_limit;
uint32_t enc_piobuf_limit;
uint32_t enc_piobuf_size;
@@ -2627,6 +2628,10 @@ extern void
efx_tx_fini(
__in efx_nic_t *enp);
+/*
+ * This symbol is deprecated and will be removed.
+ * Use the field from efx_nic_cfg_t instead.
+ */
#define EFX_TXQ_MINNDESCS 512
#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
@@ -923,10 +923,10 @@ siena_tx_qcreate(
EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS);
EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs));
- EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
+ EFSYS_ASSERT(ISP2(encp->enc_txq_min_ndescs));
if (!ISP2(ndescs) ||
- (ndescs < EFX_TXQ_MINNDESCS) ||
+ (ndescs < encp->enc_txq_min_ndescs) ||
(ndescs > encp->enc_txq_max_ndescs)) {
rc = EINVAL;
goto fail1;
@@ -936,9 +936,9 @@ siena_tx_qcreate(
goto fail2;
}
for (size = 0;
- (1 << size) <= (int)(encp->enc_txq_max_ndescs / EFX_TXQ_MINNDESCS);
+ (1U << size) <= encp->enc_txq_max_ndescs / encp->enc_txq_min_ndescs;
size++)
- if ((1 << size) == (int)(ndescs / EFX_TXQ_MINNDESCS))
+ if ((1U << size) == (uint32_t)ndescs / encp->enc_txq_min_ndescs)
break;
if (id + (1 << size) >= encp->enc_buftbl_limit) {
rc = EINVAL;
@@ -195,6 +195,7 @@ hunt_board_cfg(
* descriptor writes, preventing the use of 4096 descriptor TXQs.
*/
encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
+ encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
@@ -120,6 +120,7 @@ medford2_board_cfg(
* stuffing.
*/
encp->enc_txq_max_ndescs = 2048;
+ encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
@@ -118,6 +118,7 @@ medford_board_cfg(
* stuffing.
*/
encp->enc_txq_max_ndescs = 2048;
+ encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
@@ -24,6 +24,9 @@ extern "C" {
#endif
#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << (_dcsize))
+#define SIENA_TXQ_MAXNDESCS 4096
+#define SIENA_TXQ_MINNDESCS 512
+
#define SIENA_NVRAM_CHUNK 0x80
@@ -149,7 +149,8 @@ siena_board_cfg(
encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
- encp->enc_txq_max_ndescs = 4096;
+ encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
+ encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;
encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
(encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -