From patchwork Wed Oct 3 09:03:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 45934 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7D65C5F54; Wed, 3 Oct 2018 11:04:36 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 390185B34 for ; Wed, 3 Oct 2018 11:04:27 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 5D3C3B4005A for ; Wed, 3 Oct 2018 09:04:26 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 3 Oct 2018 02:04:23 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 3 Oct 2018 02:04:22 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w9394L2u032035 for ; Wed, 3 Oct 2018 10:04:21 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 8FA821626D1 for ; Wed, 3 Oct 2018 10:04:21 +0100 (BST) From: Andrew Rybchenko To: Date: Wed, 3 Oct 2018 10:03:53 +0100 Message-ID: <1538557436-16163-7-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1538557436-16163-1-git-send-email-arybchenko@solarflare.com> References: <1538557436-16163-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24132.005 X-TM-AS-Result: No-0.078300-4.000000-10 X-TMASE-MatchedRID: MIEO2Rh1L0+LYaqu+AuRakKcYi5Qw/RVSoCG4sefl8RnerzbhugqsivV zgQREZjFHXTgyt4N7vp5F0YgUZmOAsZEoJx1HltlrDFtme53KvvUrb18dSl4GBojiQcA4mf5i0i SPy6yqRKnYtrxS0js0Pe4mjKZQvCioG/SuxLl2m2eAiCmPx4NwJuJ+Pb8n/VxSnQ4MjwaO9cqtq 5d3cxkNRIzj1ga+GnoqWJvnpFk2yikkT33oJOZ6C5o/CTN+ZpkjDIRUKsKbmCEvNR3IwSUgH3q4 sbUu6gR4d0ZCXiqxp78mtk4GvYddiTAx8myLbWyI6KkAL2A5kcMtYrw9BuTwqSmSPRgKSZMuowv JdIWQm5DDKa3G4nrLQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.078300-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24132.005 X-MDID: 1538557467-m9XXJEWFHxTD Subject: [dpdk-dev] [PATCH 6/9] net/sfc: avoid usage of prepared packets number in EF10 Rx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Number of prepared packets is good when one Rx descriptor is one packet. Introduce pending Rx descriptor pointer which points to the first not processed Rx descriptors. Rx descriptors from completed to pending have buffers ready to be passed to application. Signed-off-by: Andrew Rybchenko Reviewed-by: Ivan Malov --- drivers/net/sfc/sfc_ef10_rx.c | 53 +++++++++++++++++------------------ 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/drivers/net/sfc/sfc_ef10_rx.c b/drivers/net/sfc/sfc_ef10_rx.c index d4af07d44..9c921c057 100644 --- a/drivers/net/sfc/sfc_ef10_rx.c +++ b/drivers/net/sfc/sfc_ef10_rx.c @@ -57,7 +57,7 @@ struct sfc_ef10_rxq { #define SFC_EF10_RXQ_EXCEPTION 0x4 #define SFC_EF10_RXQ_RSS_HASH 0x8 unsigned int ptr_mask; - unsigned int prepared; + unsigned int pending; unsigned int completed; unsigned int evq_read_ptr; efx_qword_t *evq_hw_ring; @@ -187,15 +187,14 @@ sfc_ef10_rx_prefetch_next(struct sfc_ef10_rxq *rxq, unsigned int next_id) } static struct rte_mbuf ** -sfc_ef10_rx_prepared(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts, - uint16_t nb_pkts) +sfc_ef10_rx_pending(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts) { - uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->prepared); + uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->pending - rxq->completed); if (n_rx_pkts != 0) { unsigned int completed = rxq->completed; - rxq->prepared -= n_rx_pkts; rxq->completed = completed + n_rx_pkts; do { @@ -225,42 +224,40 @@ sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev, struct rte_mbuf ** const rx_pkts_end) { const unsigned int ptr_mask = rxq->ptr_mask; - unsigned int completed = rxq->completed; + unsigned int pending = rxq->pending; unsigned int ready; struct sfc_ef10_rx_sw_desc *rxd; struct rte_mbuf *m; struct rte_mbuf *m0; - uint16_t n_rx_pkts; const uint8_t *pseudo_hdr; uint16_t pkt_len; - ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - completed) & + ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - pending) & EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); SFC_ASSERT(ready > 0); + rxq->pending = pending + ready; + if (rx_ev.eq_u64[0] & rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) | (1ull << ESF_DZ_RX_ECRC_ERR_LBN))) { - SFC_ASSERT(rxq->prepared == 0); - rxq->completed += ready; - while (ready-- > 0) { - rxd = &rxq->sw_ring[completed++ & ptr_mask]; + SFC_ASSERT(rxq->completed == pending); + do { + rxd = &rxq->sw_ring[pending++ & ptr_mask]; rte_mbuf_raw_free(rxd->mbuf); - } + } while (pending != rxq->pending); + rxq->completed = pending; return rx_pkts; } - n_rx_pkts = RTE_MIN(ready, rx_pkts_end - rx_pkts); - rxq->prepared = ready - n_rx_pkts; - rxq->completed += n_rx_pkts; + rxd = &rxq->sw_ring[pending++ & ptr_mask]; - rxd = &rxq->sw_ring[completed++ & ptr_mask]; - - sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask); + sfc_ef10_rx_prefetch_next(rxq, pending & ptr_mask); m = rxd->mbuf; *rx_pkts++ = m; + rxq->completed = pending; RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data)); m->rearm_data[0] = rxq->rearm_data; @@ -294,15 +291,17 @@ sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev, /* Remember mbuf to copy offload flags and packet type from */ m0 = m; - for (--ready; ready > 0; --ready) { - rxd = &rxq->sw_ring[completed++ & ptr_mask]; + while (pending != rxq->pending) { + rxd = &rxq->sw_ring[pending++ & ptr_mask]; - sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask); + sfc_ef10_rx_prefetch_next(rxq, pending & ptr_mask); m = rxd->mbuf; - if (ready > rxq->prepared) + if (rx_pkts != rx_pkts_end) { *rx_pkts++ = m; + rxq->completed = pending; + } RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data)); @@ -366,7 +365,7 @@ sfc_ef10_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) unsigned int evq_old_read_ptr; efx_qword_t rx_ev; - rx_pkts = sfc_ef10_rx_prepared(rxq, rx_pkts, nb_pkts); + rx_pkts = sfc_ef10_rx_pending(rxq, rx_pkts, nb_pkts); if (unlikely(rxq->flags & (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION))) @@ -601,8 +600,8 @@ sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr) { struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq); - SFC_ASSERT(rxq->prepared == 0); SFC_ASSERT(rxq->completed == 0); + SFC_ASSERT(rxq->pending == 0); SFC_ASSERT(rxq->added == 0); sfc_ef10_rx_qrefill(rxq); @@ -650,15 +649,13 @@ sfc_ef10_rx_qpurge(struct sfc_dp_rxq *dp_rxq) unsigned int i; struct sfc_ef10_rx_sw_desc *rxd; - rxq->prepared = 0; - for (i = rxq->completed; i != rxq->added; ++i) { rxd = &rxq->sw_ring[i & rxq->ptr_mask]; rte_mbuf_raw_free(rxd->mbuf); rxd->mbuf = NULL; } - rxq->completed = rxq->added = 0; + rxq->completed = rxq->pending = rxq->added = 0; rxq->flags &= ~SFC_EF10_RXQ_STARTED; }