From patchwork Mon Sep 24 13:50:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 45210 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 10C2C4F9B; Mon, 24 Sep 2018 15:51:11 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 0BDF52B9D for ; Mon, 24 Sep 2018 15:50:52 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id A05A8B400B9 for ; Mon, 24 Sep 2018 13:50:50 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 24 Sep 2018 06:50:47 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 24 Sep 2018 06:50:47 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w8ODojHF014550; Mon, 24 Sep 2018 14:50:45 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id C71D91626D2; Mon, 24 Sep 2018 14:50:45 +0100 (BST) From: Andrew Rybchenko To: CC: Richard Houldsworth Date: Mon, 24 Sep 2018 14:50:26 +0100 Message-ID: <1537797030-26548-8-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1537797030-26548-1-git-send-email-arybchenko@solarflare.com> References: <1537797030-26548-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24114.005 X-TM-AS-Result: No-1.848000-4.000000-10 X-TMASE-MatchedRID: Wv0/mEfewaGTXOTGJq49DAPZZctd3P4BlIsQ0nJjgWML2UrpDbWdp4Ep JRcbelqd93LsYxp0JcCAMuqetGVetnyef22ep6XYro1URZJFbJtGW/7KgHcM6LXDc6hxfkqGNKB AjViIIxIs7ZocpDq0Zq8cJa1DNEcNmkzUUy+sIkqrriR5JYV4H9oo13AmoUBs+1qDHV+Vs3Hw7J xwU0EvZMqEROLb/+yO4/0Jvn0rwAJmtL4Dw+zNb0D/MIf9Orkd X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10-1.848000-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24114.005 X-MDID: 1537797051-IKH05er4QZu7 Subject: [dpdk-dev] [PATCH 07/11] net/sfc/base: infer port mode bandwidth from max link speed X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Richard Houldsworth Limit the port mode bandwidth calculations by the maximum reported link speed. This system detects 25G vs 10G cards, and 100G port modes vs 40G. Signed-off-by: Richard Houldsworth Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_nic.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c index 8cd76d690..c197ff957 100644 --- a/drivers/net/sfc/base/ef10_nic.c +++ b/drivers/net/sfc/base/ef10_nic.c @@ -133,9 +133,11 @@ ef10_nic_get_port_mode_bandwidth( { uint32_t port_modes; uint32_t current_mode; - uint32_t single_lane = 10000; - uint32_t dual_lane = 50000; - uint32_t quad_lane = 40000; + efx_port_t *epp = &(enp->en_port); + + uint32_t single_lane; + uint32_t dual_lane; + uint32_t quad_lane; uint32_t bandwidth; efx_rc_t rc; @@ -145,6 +147,21 @@ ef10_nic_get_port_mode_bandwidth( goto fail1; } + if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX)) + single_lane = 25000; + else + single_lane = 10000; + + if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX)) + dual_lane = 50000; + else + dual_lane = 20000; + + if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX)) + quad_lane = 100000; + else + quad_lane = 40000; + switch (current_mode) { case TLV_PORT_MODE_1x1_NA: /* mode 0 */ bandwidth = single_lane;