On 9/13/2018 12:35 PM, Igor Russkikh wrote:
> From: Pavel Belous <pavel.belous@aquantia.com>
>
> Makefile/meson build infrastructure, atl_ethdev minimal skeleton,
> header with aquantia aQtion NIC device and vendor IDs.
>
> Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com>
> ---
> config/common_base | 9 +
> drivers/net/Makefile | 2 +
> drivers/net/atlantic/Makefile | 36 +++
> drivers/net/atlantic/atl_common.h | 96 ++++++++
> drivers/net/atlantic/atl_ethdev.c | 281 ++++++++++++++++++++++
> drivers/net/atlantic/atl_ethdev.h | 28 +++
> drivers/net/atlantic/meson.build | 19 ++
> drivers/net/atlantic/rte_pmd_atlantic_version.map | 4 +
> drivers/net/meson.build | 1 +
> mk/rte.app.mk | 1 +
<...>
> @@ -635,6 +635,15 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
> CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
>
> #
> +# Compile Aquantia Atlantic PMD driver
> +#
> +CONFIG_RTE_LIBRTE_ATLANTIC_PMD=y
> +CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG=n
We are trying to have as less compile time option as possible. Instead of
CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG compile time option, it is possible to use
dynamic logging, please switch to it.
> +CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG_RX=n
> +CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG_TX=n
> +CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG_TX_FREE=n
RX, TX & TX_FREE config options are for data path, needs to be compile time
option to not affect performance. But as far as I can see they are not used at
all, please remove them and can be added back if needed.
> +
> +#
> # Compile raw device support
> # EXPERIMENTAL: API may change without prior notice
> #
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 664398de9..3d4a1ae59 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -70,4 +70,6 @@ $(error "RTE_LIBRTE_CFGFILE must be enabled in configuration!")
> endif
> endif
>
> +DIRS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atlantic
Please add to above block alphabetically, these are kind of peculiar ones with
extra dependencies.
<...>
> +
> +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
> +LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_hash
> +LDLIBS += -lrte_bus_pci
It is hard to really know if these dependencies exists if you add them all in
initial patch, it is good to add when real dependency occurs, so that we will
know what are not needed here.
> +
> +#
> +# Add extra flags for base driver files (also known as shared code)
> +# to disable warnings in them
> +#
> +BASE_DRIVER_OBJS=$(sort $(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c))))
You don't have "base" folder, the name of your base folder seems "hw_atl". If it
not a specific name or maintenance cost you can rename it to "base" to be
consistent with other PMDs.
<...>
> @@ -0,0 +1,281 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Aquantia Corporation
> + */
> +
> +#include "atl_ethdev.h"
> +
> +#include <sys/queue.h>
> +#include <stdio.h>
> +#include <errno.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include <unistd.h>
> +#include <stdarg.h>
> +#include <inttypes.h>
> +#include <netinet/in.h>
> +#include <rte_byteorder.h>
> +#include <rte_common.h>
> +#include <rte_cycles.h>
> +
> +#include <rte_interrupts.h>
> +#include <rte_log.h>
> +#include <rte_debug.h>
> +#include <rte_pci.h>
> +#include <rte_bus_pci.h>
> +#include <rte_atomic.h>
> +#include <rte_branch_prediction.h>
> +#include <rte_memory.h>
> +#include <rte_eal.h>
> +#include <rte_alarm.h>
> +#include <rte_ether.h>
> +#include <rte_ethdev_driver.h>
> +#include <rte_ethdev_pci.h>
> +#include <rte_malloc.h>
> +#include <rte_random.h>
> +#include <rte_dev.h>
> +#include <rte_hash_crc.h>
> +#include <rte_net.h>
This is a long include list, I wonder if this is copy paste or real need. If
you/we get these with extra clutter at first place, it will be harder to clean
(if somebody spends time for it) later. Please include only what you need in
_this_ patch.
> +
> +#include "atl_common.h"
> +#include "atl_hw_regs.h"
> +#include "atl_logs.h"
> +
> +static int eth_atl_dev_init(struct rte_eth_dev *eth_dev);
> +static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev);
> +
> +static int atl_dev_configure(struct rte_eth_dev *dev);
> +static int atl_dev_start(struct rte_eth_dev *dev);
> +static void atl_dev_stop(struct rte_eth_dev *dev);
> +static void atl_dev_close(struct rte_eth_dev *dev);
> +static int atl_dev_reset(struct rte_eth_dev *dev);
> +
> +static int atl_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
> + uint16_t queue_id,
> + uint8_t stat_idx,
> + uint8_t is_rx);
Can you please add function declarations on the patch that has function
implementation.
<...>
> +static int
> +atl_get_bus_info(struct aq_hw_s *hw)
> +{
> + hw->bus.speed = atl_bus_speed_unknown;
> + hw->bus.width = atl_bus_width_unknown;
atl_bus_speed_unknown & atl_bus_width_unknown not defined in this patch breking
build. They look like enum items, please prefer uppercase names for enums.
> +
> + return 0;
> +}
> +
> +static int
> +eth_atl_dev_init(struct rte_eth_dev *eth_dev)
> +{
> + struct atl_adapter *adapter =
> + (struct atl_adapter *)eth_dev->data->dev_private;
> + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
> + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
> + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
> + int err = 0;
> +
> + eth_dev->dev_ops = &atl_eth_dev_ops;
> + eth_dev->rx_pkt_burst = &atl_recv_pkts;
> + eth_dev->tx_pkt_burst = &atl_xmit_pkts;
> + eth_dev->tx_pkt_prepare = &atl_prep_pkts;
These functions are not defined in this patch.
> +
> + /* For secondary processes, the primary process has done all the work */
> + if (rte_eal_process_type() != RTE_PROC_PRIMARY)
> + return 0;
Won't you want rx_pkt_burst & tx_pkt_burst etc to be set in secondary process?
<...>
> +static int
> +atl_dev_configure(struct rte_eth_dev *dev)
> +{
> + struct atl_interrupt *intr =
> + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
I would expect you to get compiler warning becase intr is not used, you can drop
it if you won't use.
<...>
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Aquantia Corporation
> + */
> +
> +#ifndef _ATLANTIC_ETHDEV_H_
> +#define _ATLANTIC_ETHDEV_H_
> +#include <rte_time.h>
> +#include <rte_hash.h>
> +#include <rte_pci.h>
> +#include <rte_bus_pci.h>
> +#include <rte_tm_driver.h>
> +
> +#include "atl_types.h"
This header file is *not* provided in thi patch. Please remember, each path must
be compilable. Please be sure to check patch by patch build test before sending.
<...>
> @@ -0,0 +1,19 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Aquantia Corporation
> +
> +#subdir('hw_atl')
> +
> +sources = files(
> + 'atl_ethdev.c',
> +)
> +
> +deps += ['hash', 'eal']
Why hash?
<...>
> @@ -0,0 +1,4 @@
> +DPDK_18.05 {
> +
> + local: *;
> +};
DPDK_18.11
@@ -635,6 +635,15 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
#
+# Compile Aquantia Atlantic PMD driver
+#
+CONFIG_RTE_LIBRTE_ATLANTIC_PMD=y
+CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG=n
+CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_ATLANTIC_DEBUG_TX_FREE=n
+
+#
# Compile raw device support
# EXPERIMENTAL: API may change without prior notice
#
@@ -70,4 +70,6 @@ $(error "RTE_LIBRTE_CFGFILE must be enabled in configuration!")
endif
endif
+DIRS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atlantic
+
include $(RTE_SDK)/mk/rte.subdir.mk
new file mode 100644
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Aquantia Corporation
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_pmd_atlantic.a
+
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+
+EXPORT_MAP := rte_pmd_atlantic_version.map
+
+LIBABIVER := 1
+
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_hash
+LDLIBS += -lrte_bus_pci
+
+#
+# Add extra flags for base driver files (also known as shared code)
+# to disable warnings in them
+#
+BASE_DRIVER_OBJS=$(sort $(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c))))
+$(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))
+
+VPATH += $(SRCDIR)/hw_atl
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c
+
+include $(RTE_SDK)/mk/rte.lib.mk
new file mode 100644
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Aquantia Corporation
+ */
+
+#ifndef AQ_COMMON_H
+#define AQ_COMMON_H
+
+#define ATL_PMD_DRIVER_VERSION "0.4.1"
+
+#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
+
+#define AQ_DEVICE_ID_0001 0x0001
+#define AQ_DEVICE_ID_D100 0xD100
+#define AQ_DEVICE_ID_D107 0xD107
+#define AQ_DEVICE_ID_D108 0xD108
+#define AQ_DEVICE_ID_D109 0xD109
+
+#define AQ_DEVICE_ID_AQC100 0x00B1
+#define AQ_DEVICE_ID_AQC107 0x07B1
+#define AQ_DEVICE_ID_AQC108 0x08B1
+#define AQ_DEVICE_ID_AQC109 0x09B1
+#define AQ_DEVICE_ID_AQC111 0x11B1
+#define AQ_DEVICE_ID_AQC112 0x12B1
+
+#define AQ_DEVICE_ID_AQC100S 0x80B1
+#define AQ_DEVICE_ID_AQC107S 0x87B1
+#define AQ_DEVICE_ID_AQC108S 0x88B1
+#define AQ_DEVICE_ID_AQC109S 0x89B1
+#define AQ_DEVICE_ID_AQC111S 0x91B1
+#define AQ_DEVICE_ID_AQC112S 0x92B1
+
+#define AQ_DEVICE_ID_AQC111E 0x51B1
+#define AQ_DEVICE_ID_AQC112E 0x52B1
+
+#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter"
+
+#define AQ_HWREV_ANY 0
+#define AQ_HWREV_1 1
+#define AQ_HWREV_2 2
+
+#define AQ_NIC_RATE_10G BIT(0)
+#define AQ_NIC_RATE_5G BIT(1)
+#define AQ_NIC_RATE_5G5R BIT(2)
+#define AQ_NIC_RATE_2G5 BIT(3)
+#define AQ_NIC_RATE_1G BIT(4)
+#define AQ_NIC_RATE_100M BIT(5)
+
+#define AQ_NIC_RATE_EEE_10G BIT(6)
+#define AQ_NIC_RATE_EEE_5G BIT(7)
+#define AQ_NIC_RATE_EEE_2G5 BIT(8)
+#define AQ_NIC_RATE_EEE_1G BIT(9)
+
+
+#define ATL_MAX_RING_DESC (8 * 1024 - 8)
+#define ATL_MIN_RING_DESC 32
+#define ATL_RXD_ALIGN 8
+#define ATL_TXD_ALIGN 8
+#define ATL_TX_MAX_SEG 16
+
+#define ATL_MAX_INTR_QUEUE_NUM 15
+
+#define ATL_MISC_VEC_ID 10
+#define ATL_RX_VEC_START 0
+
+#define AQ_NIC_WOL_ENABLED BIT(0)
+
+
+#define AQ_NIC_FC_OFF 0U
+#define AQ_NIC_FC_TX 1U
+#define AQ_NIC_FC_RX 2U
+#define AQ_NIC_FC_FULL 3U
+#define AQ_NIC_FC_AUTO 4U
+
+
+#define AQ_CFG_TX_FRAME_MAX (16U * 1024U)
+#define AQ_CFG_RX_FRAME_MAX (2U * 1024U)
+
+#define AQ_HW_MULTICAST_ADDRESS_MAX 32
+#define AQ_HW_MAX_SEGS_SIZE 40
+
+#define AQ_HW_MAX_RX_QUEUES 8
+#define AQ_HW_MAX_TX_QUEUES 8
+#define AQ_HW_MIN_RX_RING_SIZE 512
+#define AQ_HW_MAX_RX_RING_SIZE 8192
+#define AQ_HW_MIN_TX_RING_SIZE 512
+#define AQ_HW_MAX_TX_RING_SIZE 8192
+
+#define ATL_DEFAULT_RX_FREE_THRESH 64
+#define ATL_DEFAULT_TX_FREE_THRESH 64
+
+#define ATL_IRQ_CAUSE_LINK 0x8
+
+#define AQ_HW_LED_BLINK 0x2U
+#define AQ_HW_LED_DEFAULT 0x0U
+
+#endif /* AQ_COMMON_H */
new file mode 100644
@@ -0,0 +1,281 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Aquantia Corporation
+ */
+
+#include "atl_ethdev.h"
+
+#include <sys/queue.h>
+#include <stdio.h>
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdarg.h>
+#include <inttypes.h>
+#include <netinet/in.h>
+#include <rte_byteorder.h>
+#include <rte_common.h>
+#include <rte_cycles.h>
+
+#include <rte_interrupts.h>
+#include <rte_log.h>
+#include <rte_debug.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+#include <rte_atomic.h>
+#include <rte_branch_prediction.h>
+#include <rte_memory.h>
+#include <rte_eal.h>
+#include <rte_alarm.h>
+#include <rte_ether.h>
+#include <rte_ethdev_driver.h>
+#include <rte_ethdev_pci.h>
+#include <rte_malloc.h>
+#include <rte_random.h>
+#include <rte_dev.h>
+#include <rte_hash_crc.h>
+#include <rte_net.h>
+
+#include "atl_common.h"
+#include "atl_hw_regs.h"
+#include "atl_logs.h"
+
+static int eth_atl_dev_init(struct rte_eth_dev *eth_dev);
+static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev);
+
+static int atl_dev_configure(struct rte_eth_dev *dev);
+static int atl_dev_start(struct rte_eth_dev *dev);
+static void atl_dev_stop(struct rte_eth_dev *dev);
+static void atl_dev_close(struct rte_eth_dev *dev);
+static int atl_dev_reset(struct rte_eth_dev *dev);
+
+static int atl_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
+ uint16_t queue_id,
+ uint8_t stat_idx,
+ uint8_t is_rx);
+
+
+static void atl_dev_info_get(struct rte_eth_dev *dev,
+ struct rte_eth_dev_info *dev_info);
+
+static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev);
+
+static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev);
+static int eth_atl_pci_remove(struct rte_pci_device *pci_dev);
+
+int atl_logtype_init;
+int atl_logtype_driver;
+
+/*
+ * The set of PCI devices this driver supports
+ */
+static const struct rte_pci_id pci_id_atl_map[] = {
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_0001) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D100) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D107) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D108) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D109) },
+
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC100) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC107) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC108) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC109) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112) },
+
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC100S) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC107S) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC108S) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC109S) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111S) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112S) },
+
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111E) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112E) },
+ { .vendor_id = 0, /* sentinel */ },
+};
+
+static struct rte_pci_driver rte_atl_pmd = {
+ .id_table = pci_id_atl_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
+ RTE_PCI_DRV_IOVA_AS_VA,
+ .probe = eth_atl_pci_probe,
+ .remove = eth_atl_pci_remove,
+};
+
+static const struct rte_eth_desc_lim rx_desc_lim = {
+ .nb_max = ATL_MAX_RING_DESC,
+ .nb_min = ATL_MIN_RING_DESC,
+ .nb_align = ATL_RXD_ALIGN,
+};
+
+static const struct rte_eth_desc_lim tx_desc_lim = {
+ .nb_max = ATL_MAX_RING_DESC,
+ .nb_min = ATL_MIN_RING_DESC,
+ .nb_align = ATL_TXD_ALIGN,
+ .nb_seg_max = ATL_TX_MAX_SEG,
+ .nb_mtu_seg_max = ATL_TX_MAX_SEG,
+};
+
+static const struct eth_dev_ops atl_eth_dev_ops = {
+ .dev_configure = atl_dev_configure,
+ .dev_start = atl_dev_start,
+ .dev_stop = atl_dev_stop,
+ .dev_close = atl_dev_close,
+ .dev_reset = atl_dev_reset,
+};
+
+
+static int
+atl_get_bus_info(struct aq_hw_s *hw)
+{
+ hw->bus.speed = atl_bus_speed_unknown;
+ hw->bus.width = atl_bus_width_unknown;
+
+ return 0;
+}
+
+static int
+eth_atl_dev_init(struct rte_eth_dev *eth_dev)
+{
+ struct atl_adapter *adapter =
+ (struct atl_adapter *)eth_dev->data->dev_private;
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
+ int err = 0;
+
+ eth_dev->dev_ops = &atl_eth_dev_ops;
+ eth_dev->rx_pkt_burst = &atl_recv_pkts;
+ eth_dev->tx_pkt_burst = &atl_xmit_pkts;
+ eth_dev->tx_pkt_prepare = &atl_prep_pkts;
+
+ /* For secondary processes, the primary process has done all the work */
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ return err;
+}
+
+static int
+eth_atl_dev_uninit(struct rte_eth_dev *eth_dev)
+{
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct aq_hw_s *hw;
+
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return -EPERM;
+
+ eth_dev->dev_ops = NULL;
+ eth_dev->rx_pkt_burst = NULL;
+ eth_dev->tx_pkt_burst = NULL;
+
+ return 0;
+}
+
+static int
+eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ return rte_eth_dev_pci_generic_probe(pci_dev,
+ sizeof(struct atl_adapter), eth_atl_dev_init);
+}
+
+static int
+eth_atl_pci_remove(struct rte_pci_device *pci_dev)
+{
+ return rte_eth_dev_pci_generic_remove(pci_dev, eth_atl_dev_uninit);
+}
+
+static int
+atl_dev_configure(struct rte_eth_dev *dev)
+{
+ struct atl_interrupt *intr =
+ ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
+
+ return 0;
+}
+
+/*
+ * Configure device link speed and setup link.
+ * It returns 0 on success.
+ */
+static int
+atl_dev_start(struct rte_eth_dev *dev)
+{
+ struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ uint32_t intr_vector = 0;
+ uint32_t *link_speeds;
+ uint32_t speed = 0;
+ int vlan_mask = 0;
+ int status;
+ int err;
+
+ /* check and configure queue intr-vector mapping */
+ if ((rte_intr_cap_multiple(intr_handle) ||
+ !RTE_ETH_DEV_SRIOV(dev).active) &&
+ dev->data->dev_conf.intr_conf.rxq != 0) {
+ intr_vector = dev->data->nb_rx_queues;
+ if (intr_vector > ATL_MAX_INTR_QUEUE_NUM)
+ return -ENOTSUP;
+ if (rte_intr_efd_enable(intr_handle, intr_vector))
+ return -1;
+ }
+
+ if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
+ intr_handle->intr_vec = rte_zmalloc("intr_vec",
+ dev->data->nb_rx_queues * sizeof(int), 0);
+ if (intr_handle->intr_vec == NULL)
+ return -ENOMEM;
+ }
+
+ return 0;
+
+error:
+ atl_stop_queues(dev);
+ return -EIO;
+}
+
+/*
+ * Stop device: disable rx and tx functions to allow for reconfiguring.
+ */
+static void
+atl_dev_stop(struct rte_eth_dev *dev)
+{
+}
+
+/*
+ * Reset and stop device.
+ */
+static void
+atl_dev_close(struct rte_eth_dev *dev)
+{
+ struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+ PMD_INIT_FUNC_TRACE();
+
+ atl_dev_stop(dev);
+ hw->adapter_stopped = 1;
+}
+
+static int
+atl_dev_reset(struct rte_eth_dev *dev)
+{
+ int ret;
+
+ ret = eth_atl_dev_uninit(dev);
+ if (ret)
+ return ret;
+
+ ret = eth_atl_dev_init(dev);
+
+ return ret;
+}
+
+RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map);
+RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic");
new file mode 100644
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Aquantia Corporation
+ */
+
+#ifndef _ATLANTIC_ETHDEV_H_
+#define _ATLANTIC_ETHDEV_H_
+#include <rte_time.h>
+#include <rte_hash.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+#include <rte_tm_driver.h>
+
+#include "atl_types.h"
+#include "hw_atl/hw_atl_utils.h"
+
+#define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
+#define ATL_FLAG_NEED_LINK_CONFIG (uint32_t)(4 << 0)
+
+/*
+ * Structure to store private data for each driver instance (for each port).
+ */
+struct atl_adapter {
+};
+
+#define ATL_DEV_TO_ADAPTER(dev) \
+ ((struct atl_adapter *)(dev)->data->dev_private)
+
+#endif /* _ATLANTIC_ETHDEV_H_ */
new file mode 100644
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Aquantia Corporation
+
+#subdir('hw_atl')
+
+sources = files(
+ 'atl_ethdev.c',
+)
+
+deps += ['hash', 'eal']
+
+if get_option('buildtype') == 'debug'
+ dpdk_conf.set('RTE_LIBRTE_ATLANTIC_DEBUG', 1)
+ dpdk_conf.set('RTE_LIBRTE_ATLANTIC_DEBUG_RX', 1)
+ dpdk_conf.set('RTE_LIBRTE_ATLANTIC_DEBUG_TX', 1)
+ dpdk_conf.set('RTE_LIBRTE_ATLANTIC_DEBUG_TX_FREE', 1)
+endif
+
+allow_experimental_apis = true
new file mode 100644
@@ -0,0 +1,4 @@
+DPDK_18.05 {
+
+ local: *;
+};
@@ -3,6 +3,7 @@
drivers = ['af_packet',
'ark',
+ 'atlantic',
'avp',
'axgbe', 'bonding',
'bnx2x',
@@ -153,6 +153,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += -lrte_pmd_mlx5 -ldl -lmnl
else
_LDLIBS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += -lrte_pmd_mlx5 -libverbs -lmlx5 -lmnl
endif
+_LDLIBS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += -lrte_pmd_atlantic
_LDLIBS-$(CONFIG_RTE_LIBRTE_MVPP2_PMD) += -lrte_pmd_mvpp2 -L$(LIBMUSDK_PATH)/lib -lmusdk
_LDLIBS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += -lrte_pmd_nfp
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += -lrte_pmd_null