From patchwork Wed Aug 29 07:45:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 43946 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AF4924C9C; Wed, 29 Aug 2018 09:45:54 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 731FE2B92; Wed, 29 Aug 2018 09:45:52 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 3FA9114006B; Wed, 29 Aug 2018 07:45:51 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 29 Aug 2018 00:45:48 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 29 Aug 2018 00:45:48 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w7T7jkTn028739; Wed, 29 Aug 2018 08:45:46 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 614B31626D1; Wed, 29 Aug 2018 08:45:46 +0100 (BST) From: Andrew Rybchenko To: Gaetan Rivet CC: , Igor Romanov , Date: Wed, 29 Aug 2018 08:45:36 +0100 Message-ID: <1535528736-31325-1-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24060.005 X-TM-AS-Result: No-2.805800-4.000000-10 X-TMASE-MatchedRID: P5PncPndUjwpz7oBrDd6ebMsPmSZxbpkJGh48zigYxV3vUA6/Pi03KUe OyMwcLeGrLrdQysupgzWcqMMF5OoNNF/tAhYTSzXX/6lQb2s9WFWOQQSa4vbHZsoi2XrUn/Jn6K dMrRsL14qtq5d3cxkNTD4CBuRQ42eXBK6OfqxD9cN3O16YH4zll+cRWV6ENKU5oMgg/K9UIjkf0 /fzoyAX9F35X9tProBRHtyixTKh41kFxuHGCKQH7BIxDLzcTJCOKBkFAm8GOUPoO5ncI6OuehbQ 2QpmASdbcuA3Id6O6JDDKa3G4nrLQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.805800-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24060.005 X-MDID: 1535528752-521GS0U_6YUy Subject: [dpdk-dev] [PATCH] net/failsafe: limit device capabilities to really supported X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Romanov Failsafe driver does not support any device capabilities yet. Make fs_dev_infos_get() consider default ones to limit advertised device capabilities to really supported instead of unconditional inheritance from sub-devices. Fixes: cac923cfea47 ("ethdev: support runtime queue setup") Cc: stable@dpdk.org Signed-off-by: Igor Romanov Signed-off-by: Andrew Rybchenko Acked-by: Gaetan Rivet --- drivers/net/failsafe/failsafe_ops.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/failsafe/failsafe_ops.c b/drivers/net/failsafe/failsafe_ops.c index 24e91c931..2df8b55d9 100644 --- a/drivers/net/failsafe/failsafe_ops.c +++ b/drivers/net/failsafe/failsafe_ops.c @@ -716,6 +716,8 @@ fs_stats_reset(struct rte_eth_dev *dev) * all sub_devices and the default capabilities. * Uses a logical AND of TX capabilities among * the active probed sub_device and the default capabilities. + * Uses a logical AND of device capabilities among + * all sub_devices and the default capabilities. * */ static void @@ -734,10 +736,12 @@ fs_dev_infos_get(struct rte_eth_dev *dev, uint64_t rx_offload_capa; uint64_t rxq_offload_capa; uint64_t rss_hf_offload_capa; + uint64_t dev_capa; rx_offload_capa = default_infos.rx_offload_capa; rxq_offload_capa = default_infos.rx_queue_offload_capa; rss_hf_offload_capa = default_infos.flow_type_rss_offloads; + dev_capa = default_infos.dev_capa; FOREACH_SUBDEV_STATE(sdev, i, dev, DEV_PROBED) { rte_eth_dev_info_get(PORT_ID(sdev), &PRIV(dev)->infos); @@ -746,12 +750,14 @@ fs_dev_infos_get(struct rte_eth_dev *dev, PRIV(dev)->infos.rx_queue_offload_capa; rss_hf_offload_capa &= PRIV(dev)->infos.flow_type_rss_offloads; + dev_capa &= PRIV(dev)->infos.dev_capa; } sdev = TX_SUBDEV(dev); rte_eth_dev_info_get(PORT_ID(sdev), &PRIV(dev)->infos); PRIV(dev)->infos.rx_offload_capa = rx_offload_capa; PRIV(dev)->infos.rx_queue_offload_capa = rxq_offload_capa; PRIV(dev)->infos.flow_type_rss_offloads = rss_hf_offload_capa; + PRIV(dev)->infos.dev_capa = dev_capa; PRIV(dev)->infos.tx_offload_capa &= default_infos.tx_offload_capa; PRIV(dev)->infos.tx_queue_offload_capa &=