From patchwork Fri Aug 24 18:30:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 43890 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9471B1B082; Fri, 24 Aug 2018 20:30:37 +0200 (CEST) Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by dpdk.org (Postfix) with ESMTP id BEE9D1B074 for ; Fri, 24 Aug 2018 20:30:32 +0200 (CEST) Received: by mail-lj1-f194.google.com with SMTP id 203-v6so7561951ljj.13 for ; Fri, 24 Aug 2018 11:30:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w1db2MwYke5E6b/UWoQugpuGwBGm8UBRDJS1sJSavl0=; b=NWH3jM4XrWc7QTSo6dglX79zEzaxbj/w/46dxO5aqWn87wYSvQV7JNtYbEo6C0Xv52 SboUtQFWimbKvGY/dyIwMSHEDr7d25vVmOdUkEpSQuMKgqcEsjMRd738i72kd2Lla480 A4cYwydeeCh0ypzrs3NWo/ODnxQE3S7LaHYmePsH5JGviz2ZAE9+ewIkTehcJDcrpun8 bGCQ1mQgHiZ8xpmiw8fnBoXEdqQpHfGooyG2rJeMUNm54jwCoqjVwEf1Lt1CeO+oNQ9Z jNBgDgINMB86hDjMOIIjVdZi84z7/KRukT32hoeFGjLctEJN+mi+362HpEACyN0wiIUe Yv4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w1db2MwYke5E6b/UWoQugpuGwBGm8UBRDJS1sJSavl0=; b=fU+uT3dgb5tYrNx8AtUDiJvw0Mv02yzBLGBD06QL+Fna9gwy/XIT1oH+3bLUtm/JsO cF6BehFJsnzGKYbxMHiVol+FknHZxUvSOqubtA4HYTvPFoXyYxqc8dgTAkxUdpsvAIDn RlOx83nAsITTpqAEkhyGo/KXgGpi+4xMzVG+jbBFjhI15kc10yZkXm8CxeotgggdbIHJ ynGzrrRXoSEHK0e7eJCqPqgI1+D88f9BvxATSi8wZ5V2huR7qO+mpxtRkyPO2KHNCJbE xjnsGf0dh6cKbterdv/chWMHMntbRZjR2I+8zAJG7f5c9XvmriB+zqHlNw2QTAX6TpwE S1bw== X-Gm-Message-State: APzg51D0DVB5eAXPneCUn4jbrOju2GPA+ucwWTsf8mXNv286NjDaCHTx VBIjYSmzHamwsa28yMIGxRlg6U1rtfA= X-Google-Smtp-Source: ANB0Vdbn4lxNSEn/6O5gToNd9DIBL4AouRVeKHzA4lwK7tx2suQ9CMuMv68a03jERjoW8DkqWr3E0g== X-Received: by 2002:a2e:8147:: with SMTP id t7-v6mr2235792ljg.32.1535135432235; Fri, 24 Aug 2018 11:30:32 -0700 (PDT) Received: from sh.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id g16-v6sm1420484lfb.5.2018.08.24.11.30.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 11:30:31 -0700 (PDT) From: Tomasz Duszynski To: dev@dpdk.org Cc: nsamsono@marvell.com, mw@semihalf.com Date: Fri, 24 Aug 2018 20:30:03 +0200 Message-Id: <1535135403-16115-7-git-send-email-tdu@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535135403-16115-1-git-send-email-tdu@semihalf.com> References: <1535122494-30249-1-git-send-email-tdu@semihalf.com> <1535135403-16115-1-git-send-email-tdu@semihalf.com> Subject: [dpdk-dev] [PATCH v3 6/6] net/mvpp2: add VLAN packet type support for parser offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Natalie Samsonov Add VLAN packet type support for parser offload. Signed-off-by: Natalie Samsonov Reviewed-by: Shlomi Gridish Reviewed-by: Dmitri Epshtein Reviewed-by: Yuval Caduri --- drivers/net/mvpp2/mrvl_ethdev.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 6f18315..6824445 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1353,6 +1353,8 @@ mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) { static const uint32_t ptypes[] = { RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L2_ETHER_VLAN, + RTE_PTYPE_L2_ETHER_QINQ, RTE_PTYPE_L3_IPV4, RTE_PTYPE_L3_IPV4_EXT, RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, @@ -1922,13 +1924,27 @@ mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, { enum pp2_inq_l3_type l3_type; enum pp2_inq_l4_type l4_type; + enum pp2_inq_vlan_tag vlan_tag; uint64_t packet_type; pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); + pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); packet_type = RTE_PTYPE_L2_ETHER; + switch (vlan_tag) { + case PP2_INQ_VLAN_TAG_SINGLE: + packet_type |= RTE_PTYPE_L2_ETHER_VLAN; + break; + case PP2_INQ_VLAN_TAG_DOUBLE: + case PP2_INQ_VLAN_TAG_TRIPLE: + packet_type |= RTE_PTYPE_L2_ETHER_QINQ; + break; + default: + break; + } + switch (l3_type) { case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: packet_type |= RTE_PTYPE_L3_IPV4;