diff mbox series

[v2] net/ixgbe: fix Tx check descriptor status APIs error

Message ID 1529976254-72268-1-git-send-email-wei.zhao1@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers show
Series [v2] net/ixgbe: fix Tx check descriptor status APIs error | expand

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Zhao1, Wei June 26, 2018, 1:24 a.m. UTC
This is an issue involve RS bit set rule in ixgbe.
Let us take function ixgbe_xmit_pkts_vec () as an example,
in this function RS bit will be set for descriptor with index
txq->tx_next_rs, and also descriptor free function
ixgbe_tx_free_bufs() also check RS bit for descriptor with index
txq->tx_next_rs, This is perfect ok. Let us take an example,
if app set tx_rs_thresh = 32 and nb_desc = 512, then ixgbe PMD code
will init txq->tx_next_rs = 31 in function ixgbe_reset_tx_queue when
tx queue setup. And also txq->tx_next_rs will be update as 63, 95
and so on. But, in the function ixgbe_dev_tx_descriptor_status(),
the RS bit to check is " desc = ((desc + txq->tx_rs_thresh - 1) /
txq->tx_rs_thresh) * txq-tx_rs_thresh", which is 32 ,64, 96 and so on.
So, they are all wrong! In tx function of ixgbe_xmit_pkts_simple,
the RS bit rule is also the same, it also set index 31 ,64, 95.
we need to correct it.

Fixes: a2919e13d95e ("net/ixgbe: implement descriptor status API")

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>

---

v2:
-add not support case for this feature
---
 drivers/net/ixgbe/ixgbe_rxtx.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 3e13d26..087657c 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -3145,16 +3145,20 @@  ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
 	if (unlikely(offset >= txq->nb_tx_desc))
 		return -EINVAL;
 
+	if (rte_eth_devices[txq->port_id].tx_pkt_burst ==
+		ixgbe_xmit_pkts)
+		return -ENOTSUP;
+
 	desc = txq->tx_tail + offset;
+	if (desc >= txq->nb_tx_desc)
+		desc -= txq->nb_tx_desc;
 	/* go to next desc that has the RS bit */
-	desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
-		txq->tx_rs_thresh;
-	if (desc >= txq->nb_tx_desc) {
+	desc = (desc  / txq->tx_rs_thresh + 1) *
+			txq->tx_rs_thresh - 1;
+	if (desc >= txq->nb_tx_desc)
 		desc -= txq->nb_tx_desc;
-		if (desc >= txq->nb_tx_desc)
-			desc -= txq->nb_tx_desc;
-	}
 
+	desc = txq->sw_ring[desc].last_id;
 	status = &txq->tx_ring[desc].wb.status;
 	if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
 		return RTE_ETH_TX_DESC_DONE;