From patchwork Wed Apr 25 10:01:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zijie Pan X-Patchwork-Id: 38882 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E57695F51; Wed, 25 Apr 2018 12:02:32 +0200 (CEST) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by dpdk.org (Postfix) with ESMTP id 4B1795B40 for ; Wed, 25 Apr 2018 12:02:24 +0200 (CEST) Received: by mail-wm0-f67.google.com with SMTP id a8so6114558wmg.5 for ; Wed, 25 Apr 2018 03:02:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zpc60F2tnX2T6Jb88eeBs1saRtbKV3ZOpDo+oOobdaA=; b=Weco/7nEPi+0gK5264LHaibl7DThwiiHMShVA1nqKPCOYOdfqtsoSWwr0Y8NPvbFQm 2BuceWNPSywkVdMei60NodsvnNUE8fr0FxC55bwFLLvMe/spLXODAhSggWrgzuwFkKyS 9dvHkWO9A6GHYCVXIaoLbbHT30IzSnVyn/bUVNFKcwWrJppfqBSKBlQmL8u5aXbeAGq1 HoWsktz3fPdMMmR3YDB4mjXe8vz/EmSRk8eRugMxtyJa/90OUYj8zmiA0bGZs4Oz8bEr AYQrP+Marl2uPH+oOL0W6rSmuX5uRm6Iai0T7d3c7XM0GiETRJbsp833VPI89ru2Pafh 6ngw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Zpc60F2tnX2T6Jb88eeBs1saRtbKV3ZOpDo+oOobdaA=; b=DpqehSSyGly9BORTvQymJ6fYCg3NLd6QGTvm/0Z/8KnlXgzCGbhtiU/dTeUs1oM3gA oKSET0cRWDLeuu7KispdysGbu+hzsr8vw944X0kEbs2NAnWqQ9oEVdJZyDUT7+Ul7AqR /wzLFHYOv2Ev5jEQuRJpwRv/bgM3EWmGNe0vqIt+7n8vebNk6M+3tfFEBV6JnyJ/dRbN ufVaLv4UtIaeEW7f5Z/NuWeeGe32MKcDXEBJX7oDmGtdrEwBimHcGjVdzSrWvtEeSjux cRmO/qsHt6fgYQM8VDfLXnS6fjD6J7khJhSD0BYmPXTeeQvJZQaMaSV7XBQ99YwHkBjc Psvg== X-Gm-Message-State: ALQs6tB2uTcBqyvlBWekI79dEVQtVAJhatm51zNKUB4lDgnkeo1sBImI MJFUu73I8EuYp8O+LTbEcEH7qiUlJ6U= X-Google-Smtp-Source: AB8JxZoz6Qy/yiOZQoNXg8tggag0bbN1AhwGrQTGCRYMSDfl1CCkVYy13A4UqHiJsMuZylTLK8PK4g== X-Received: by 10.28.6.14 with SMTP id 14mr14269252wmg.42.1524650543777; Wed, 25 Apr 2018 03:02:23 -0700 (PDT) Received: from cougar.6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id n143sm14100363wmd.29.2018.04.25.03.02.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Apr 2018 03:02:23 -0700 (PDT) From: Zijie Pan To: dev@dpdk.org Cc: remy.horton@intel.com, ferruh.yigit@intel.com, thomas@monjalon.net, beilei.xing@intel.com, qi.z.zhang@intel.com Date: Wed, 25 Apr 2018 12:01:55 +0200 Message-Id: <1524650515-26659-6-git-send-email-zijie.pan@6wind.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1524650515-26659-1-git-send-email-zijie.pan@6wind.com> References: <1524647624-23005-1-git-send-email-zijie.pan@6wind.com> <1524650515-26659-1-git-send-email-zijie.pan@6wind.com> Subject: [dpdk-dev] [PATCH v6 5/5] net/i40e: add module EEPROM callbacks for i40e X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add new callbacks for eth_dev_ops of i40e to get the information and data of plugin module eeprom. Signed-off-by: Zijie Pan Acked-by: Remy Horton --- Cc: beilei.xing@intel.com Cc: qi.z.zhang@intel.com drivers/net/i40e/i40e_ethdev.c | 147 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 180ac74..948ee89 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -369,6 +369,11 @@ static int i40e_get_regs(struct rte_eth_dev *dev, static int i40e_get_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom); +static int i40e_get_module_info(struct rte_eth_dev *dev, + struct rte_eth_dev_module_info *modinfo); +static int i40e_get_module_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *info); + static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr); @@ -489,6 +494,8 @@ static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, .get_reg = i40e_get_regs, .get_eeprom_length = i40e_get_eeprom_length, .get_eeprom = i40e_get_eeprom, + .get_module_info = i40e_get_module_info, + .get_module_eeprom = i40e_get_module_eeprom, .mac_addr_set = i40e_set_default_mac_addr, .mtu_set = i40e_dev_mtu_set, .tm_ops_get = i40e_tm_ops_get, @@ -11327,6 +11334,146 @@ static int i40e_get_eeprom(struct rte_eth_dev *dev, return 0; } +static int i40e_get_module_info(struct rte_eth_dev *dev, + struct rte_eth_dev_module_info *modinfo) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t sff8472_comp = 0; + uint32_t sff8472_swap = 0; + uint32_t sff8636_rev = 0; + i40e_status status; + uint32_t type = 0; + + /* Check if firmware supports reading module EEPROM. */ + if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) { + PMD_DRV_LOG(ERR, + "Module EEPROM memory read not supported. " + "Please update the NVM image.\n"); + return -EINVAL; + } + + status = i40e_update_link_info(hw); + if (status) + return -EIO; + + if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) { + PMD_DRV_LOG(ERR, + "Cannot read module EEPROM memory. " + "No module connected.\n"); + return -EINVAL; + } + + type = hw->phy.link_info.module_type[0]; + + switch (type) { + case I40E_MODULE_TYPE_SFP: + status = i40e_aq_get_phy_register(hw, + I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, + I40E_I2C_EEPROM_DEV_ADDR, + I40E_MODULE_SFF_8472_COMP, + &sff8472_comp, NULL); + if (status) + return -EIO; + + status = i40e_aq_get_phy_register(hw, + I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, + I40E_I2C_EEPROM_DEV_ADDR, + I40E_MODULE_SFF_8472_SWAP, + &sff8472_swap, NULL); + if (status) + return -EIO; + + /* Check if the module requires address swap to access + * the other EEPROM memory page. + */ + if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) { + PMD_DRV_LOG(WARNING, + "Module address swap to access " + "page 0xA2 is not supported.\n"); + modinfo->type = RTE_ETH_MODULE_SFF_8079; + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; + } else if (sff8472_comp == 0x00) { + /* Module is not SFF-8472 compliant */ + modinfo->type = RTE_ETH_MODULE_SFF_8079; + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; + } else { + modinfo->type = RTE_ETH_MODULE_SFF_8472; + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; + } + break; + case I40E_MODULE_TYPE_QSFP_PLUS: + /* Read from memory page 0. */ + status = i40e_aq_get_phy_register(hw, + I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, + 0, + I40E_MODULE_REVISION_ADDR, + &sff8636_rev, NULL); + if (status) + return -EIO; + /* Determine revision compliance byte */ + if (sff8636_rev > 0x02) { + /* Module is SFF-8636 compliant */ + modinfo->type = RTE_ETH_MODULE_SFF_8636; + modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; + } else { + modinfo->type = RTE_ETH_MODULE_SFF_8436; + modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; + } + break; + case I40E_MODULE_TYPE_QSFP28: + modinfo->type = RTE_ETH_MODULE_SFF_8636; + modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; + break; + default: + PMD_DRV_LOG(ERR, "Module type unrecognized\n"); + return -EINVAL; + } + return 0; +} + +static int i40e_get_module_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *info) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + bool is_sfp = false; + i40e_status status; + uint8_t *data = info->data; + uint32_t value = 0; + uint32_t i; + + if (!info || !info->length || !data) + return -EINVAL; + + if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP) + is_sfp = true; + + for (i = 0; i < info->length; i++) { + u32 offset = i + info->offset; + u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0; + + /* Check if we need to access the other memory page */ + if (is_sfp) { + if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) { + offset -= RTE_ETH_MODULE_SFF_8079_LEN; + addr = I40E_I2C_EEPROM_DEV_ADDR2; + } + } else { + while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) { + /* Compute memory page number and offset. */ + offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2; + addr++; + } + } + status = i40e_aq_get_phy_register(hw, + I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, + addr, offset, &value, NULL); + if (status) + return -EIO; + data[i] = (uint8_t)value; + } + return 0; +} + static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr) {