diff mbox

[dpdk-dev,06/30] crypto/qat: change filename crypto to sym

Message ID 1523040732-3290-7-git-send-email-fiona.trahe@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Pablo de Lara Guarch
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail apply issues

Commit Message

Fiona Trahe April 6, 2018, 6:51 p.m. UTC 
This commit renames qat_crypto.c/h to qat_sym.c/h
And makes a few whitespace changes to resolve line-length
issues.

Signed-off-by: ArkadiuszX Kusztal <arkadiuszx.kusztal@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
 drivers/crypto/qat/Makefile                    |  2 +-
 drivers/crypto/qat/meson.build                 |  2 +-
 drivers/crypto/qat/qat_qp.c                    |  2 +-
 drivers/crypto/qat/{qat_crypto.c => qat_sym.c} | 60 +++++++++++++-------------
 drivers/crypto/qat/{qat_crypto.h => qat_sym.h} |  0
 drivers/crypto/qat/rte_qat_cryptodev.c         |  2 +-
 6 files changed, 33 insertions(+), 35 deletions(-)
 rename drivers/crypto/qat/{qat_crypto.c => qat_sym.c} (95%)
 rename drivers/crypto/qat/{qat_crypto.h => qat_sym.h} (100%)
diff mbox

Patch

diff --git a/drivers/crypto/qat/Makefile b/drivers/crypto/qat/Makefile
index c63c1515e..8cb802b9d 100644
--- a/drivers/crypto/qat/Makefile
+++ b/drivers/crypto/qat/Makefile
@@ -21,7 +21,7 @@  LDLIBS += -lrte_cryptodev
 LDLIBS += -lrte_pci -lrte_bus_pci
 
 # library source files
-SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_crypto.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_sym.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_device.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_qp.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_sym_session.c
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index be4282a83..e596006da 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -5,7 +5,7 @@  dep = dependency('libcrypto', required: false)
 if not dep.found()
 	build = false
 endif
-sources = files('qat_crypto.c', 'qat_qp.c',
+sources = files('qat_sym.c', 'qat_qp.c',
 		'qat_sym_session.c',
 		'rte_qat_cryptodev.c',
 		'qat_device.c')
diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c
index e42acd877..927c78111 100644
--- a/drivers/crypto/qat/qat_qp.c
+++ b/drivers/crypto/qat/qat_qp.c
@@ -13,7 +13,7 @@ 
 #include <rte_prefetch.h>
 
 #include "qat_logs.h"
-#include "qat_crypto.h"
+#include "qat_sym.h"
 #include "adf_transport_access_macros.h"
 
 #define ADF_MAX_SYM_DESC			4096
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_sym.c
similarity index 95%
rename from drivers/crypto/qat/qat_crypto.c
rename to drivers/crypto/qat/qat_sym.c
index 96a1b78f0..f5d542ae3 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -6,15 +6,14 @@ 
 #include <rte_mbuf.h>
 #include <rte_hexdump.h>
 #include <rte_crypto_sym.h>
-#include <rte_byteorder.h>
-#include <rte_pci.h>
 #include <rte_bus_pci.h>
+#include <rte_byteorder.h>
 
 #include <openssl/evp.h>
 
 #include "qat_logs.h"
 #include "qat_sym_session.h"
-#include "qat_crypto.h"
+#include "qat_sym.h"
 #include "adf_transport_access_macros.h"
 
 #define BYTE_LENGTH    8
@@ -500,8 +499,6 @@  qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 		return -EINVAL;
 	}
 
-
-
 	qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 	rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 	qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
@@ -512,11 +509,11 @@  qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 			ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 		/* AES-GCM or AES-CCM */
 		if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
-				ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
-				(ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
-				&& ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
-				&& ctx->qat_hash_alg ==
-						ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
+			ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
+			(ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
+			&& ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
+			&& ctx->qat_hash_alg ==
+					ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
 			do_aead = 1;
 		} else {
 			do_auth = 1;
@@ -642,7 +639,6 @@  qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 					qat_req->comn_hdr.serv_specif_flags,
 					ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 			}
-
 			set_cipher_iv(ctx->cipher_iv.length,
 					ctx->cipher_iv.offset,
 					cipher_param, op, qat_req);
@@ -650,15 +646,14 @@  qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 		} else if (ctx->qat_hash_alg ==
 				ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
 
-			/* In case of AES-CCM this may point to user selected memory
-			 * or iv offset in cypto_op
+			/* In case of AES-CCM this may point to user selected
+			 * memory or iv offset in cypto_op
 			 */
 			uint8_t *aad_data = op->sym->aead.aad.data;
 			/* This is true AAD length, it not includes 18 bytes of
 			 * preceding data
 			 */
 			uint8_t aad_ccm_real_len = 0;
-
 			uint8_t aad_len_field_sz = 0;
 			uint32_t msg_len_be =
 					rte_bswap32(op->sym->aead.data.length);
@@ -670,33 +665,36 @@  qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 					ICP_QAT_HW_CCM_AAD_LEN_INFO;
 			} else {
 				/*
-				 * aad_len not greater than 18, so no actual aad data,
-				 * then use IV after op for B0 block
+				 * aad_len not greater than 18, so no actual aad
+				 *  data, then use IV after op for B0 block
 				 */
-				aad_data = rte_crypto_op_ctod_offset(op, uint8_t *,
+				aad_data = rte_crypto_op_ctod_offset(op,
+						uint8_t *,
 						ctx->cipher_iv.offset);
 				aad_phys_addr_aead =
 						rte_crypto_op_ctophys_offset(op,
-								ctx->cipher_iv.offset);
+							ctx->cipher_iv.offset);
 			}
 
-			uint8_t q = ICP_QAT_HW_CCM_NQ_CONST - ctx->cipher_iv.length;
+			uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
+							ctx->cipher_iv.length;
 
-			aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(aad_len_field_sz,
+			aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
+							aad_len_field_sz,
 							ctx->digest_length, q);
 
 			if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
 				memcpy(aad_data	+ ctx->cipher_iv.length +
-					ICP_QAT_HW_CCM_NONCE_OFFSET
-					+ (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
-					(uint8_t *)&msg_len_be,
-					ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
+				    ICP_QAT_HW_CCM_NONCE_OFFSET +
+				    (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
+				    (uint8_t *)&msg_len_be,
+				    ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
 			} else {
 				memcpy(aad_data	+ ctx->cipher_iv.length +
-					ICP_QAT_HW_CCM_NONCE_OFFSET,
-					(uint8_t *)&msg_len_be
-					+ (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
-					- q), q);
+				    ICP_QAT_HW_CCM_NONCE_OFFSET,
+				    (uint8_t *)&msg_len_be
+				    + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
+				    - q), q);
 			}
 
 			if (aad_len_field_sz > 0) {
@@ -709,10 +707,10 @@  qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 					uint8_t pad_idx = 0;
 
 					pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
-						((aad_ccm_real_len + aad_len_field_sz) %
-							ICP_QAT_HW_CCM_AAD_B0_LEN);
+					((aad_ccm_real_len + aad_len_field_sz) %
+						ICP_QAT_HW_CCM_AAD_B0_LEN);
 					pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
-						aad_ccm_real_len + aad_len_field_sz;
+					    aad_ccm_real_len + aad_len_field_sz;
 					memset(&aad_data[pad_idx],
 							0, pad_len);
 				}
diff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_sym.h
similarity index 100%
rename from drivers/crypto/qat/qat_crypto.h
rename to drivers/crypto/qat/qat_sym.h
diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c b/drivers/crypto/qat/rte_qat_cryptodev.c
index e425eb43f..45f8a253b 100644
--- a/drivers/crypto/qat/rte_qat_cryptodev.c
+++ b/drivers/crypto/qat/rte_qat_cryptodev.c
@@ -9,7 +9,7 @@ 
 #include <rte_pci.h>
 #include <rte_cryptodev_pmd.h>
 
-#include "qat_crypto.h"
+#include "qat_sym.h"
 #include "qat_sym_session.h"
 #include "qat_logs.h"