From patchwork Wed Feb 21 14:14:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 35325 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D2F581B22A; Wed, 21 Feb 2018 15:14:35 +0100 (CET) Received: from mail-lf0-f68.google.com (mail-lf0-f68.google.com [209.85.215.68]) by dpdk.org (Postfix) with ESMTP id BEE971B1D4 for ; Wed, 21 Feb 2018 15:14:34 +0100 (CET) Received: by mail-lf0-f68.google.com with SMTP id 70so2562944lfw.2 for ; Wed, 21 Feb 2018 06:14:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IMRmcs2NYDeWlANfEieCH/QTiZEjYidy6GG1/yDAQEA=; b=ca1Mxu9vhlGOb+OmNahWU1B/Id9gCDQqSx2VY1ii0YVYHh3YxD6tdzEansEpSn7XgV X4FAzJdWWAqlV4FUzI2KS/vt2iu+2cSdCRE7HojSQwUlpZRaxVs9TMsr+j8IPJojXEgp SNaa2PG/CRc0KR+zCSm+uOdpXpxJee3y9tIHE1S83KkYmceQ/up9bgXy5xutuK2NnxTg stxh64BFpY1wsAwxMEHfclhQpGiv0NXXSzkyjAskxzaDA6CwdHK21HpWSgI6L25p+4kk ZJagXdVZk6f75UHw0PBTPMFbtiapu0ilUaGZQ2V4kIji6q52dvECYaOe3Wn50vEAMScB hQKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IMRmcs2NYDeWlANfEieCH/QTiZEjYidy6GG1/yDAQEA=; b=M5CFk7p+IZZohXDI0iQlczTywruFNMKGJPXOy2fKDFPCrm//zqYOOFieEW01FtgP6+ 5p+6YscYvImfTKvEDAE+vDdIxlAf5GsenQL7QQ+yZrfLYu47d1f5dMRC6eo+njzSoOtj rZpQEaHg+EPEZncxi0wRyNTF+HykRM9N1ZoxpRrgWEAE6r7vqx0HRcHsx7AxDivOgKu1 E8VcadbY0ZDxcolU9Tbz9UN1TQes+IcMc5Le+KARj3Tm1GE1b/o8EExytV0K2hn4PiJJ WKN2pNeMcDSpUu3mbTgUkFv/m3wesSwY/nN6kOGj6oVGJgoz6H6u+lNeUSFlJg4IdaQr Eqcg== X-Gm-Message-State: APf1xPABMf+MxiSISyNqNLwvqYPzJjKBZUAL2a7dyJOHT5nmUBDlaJgR 2SHLjCMSWI6gYuDuiGSH8BW7+Pe5Go8= X-Google-Smtp-Source: AH8x225PbAGRlXgNWTtZ+VlL007Oq7ZKe1Xq90nGdR+RTLRCJlSHpgAuFLP0eAHq1ozMuyK8KebauQ== X-Received: by 10.25.26.130 with SMTP id a124mr2307453lfa.35.1519222474072; Wed, 21 Feb 2018 06:14:34 -0800 (PST) Received: from sh.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id e27sm5038177lff.89.2018.02.21.06.14.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Feb 2018 06:14:33 -0800 (PST) From: Tomasz Duszynski To: dev@dpdk.org Cc: mw@semihalf.com, dima@marvell.com, nsamsono@marvell.com, jck@semihalf.com, Tomasz Duszynski Date: Wed, 21 Feb 2018 15:14:14 +0100 Message-Id: <1519222460-14605-3-git-send-email-tdu@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519222460-14605-1-git-send-email-tdu@semihalf.com> References: <1519222460-14605-1-git-send-email-tdu@semihalf.com> Subject: [dpdk-dev] [PATCH 2/8] net/mrvl: add ingress policer support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add ingress policer support. Signed-off-by: Natalie Samsonov Signed-off-by: Tomasz Duszynski --- drivers/net/mrvl/mrvl_ethdev.c | 6 ++ drivers/net/mrvl/mrvl_ethdev.h | 1 + drivers/net/mrvl/mrvl_qos.c | 160 +++++++++++++++++++++++++++++++++++++++-- drivers/net/mrvl/mrvl_qos.h | 3 + 4 files changed, 166 insertions(+), 4 deletions(-) diff --git a/drivers/net/mrvl/mrvl_ethdev.c b/drivers/net/mrvl/mrvl_ethdev.c index 3611a92..2d59fce 100644 --- a/drivers/net/mrvl/mrvl_ethdev.c +++ b/drivers/net/mrvl/mrvl_ethdev.c @@ -689,6 +689,12 @@ mrvl_dev_stop(struct rte_eth_dev *dev) if (priv->ppio) pp2_ppio_deinit(priv->ppio); priv->ppio = NULL; + + /* policer must be released after ppio deinitialization */ + if (priv->policer) { + pp2_cls_plcr_deinit(priv->policer); + priv->policer = NULL; + } } /** diff --git a/drivers/net/mrvl/mrvl_ethdev.h b/drivers/net/mrvl/mrvl_ethdev.h index f7afae5..0d152d6 100644 --- a/drivers/net/mrvl/mrvl_ethdev.h +++ b/drivers/net/mrvl/mrvl_ethdev.h @@ -113,6 +113,7 @@ struct mrvl_priv { struct pp2_cls_qos_tbl_params qos_tbl_params; struct pp2_cls_tbl *qos_tbl; uint16_t nb_rx_queues; + struct pp2_cls_plcr *policer; }; #endif /* _MRVL_ETHDEV_H_ */ diff --git a/drivers/net/mrvl/mrvl_qos.c b/drivers/net/mrvl/mrvl_qos.c index fbb3681..854eb4d 100644 --- a/drivers/net/mrvl/mrvl_qos.c +++ b/drivers/net/mrvl/mrvl_qos.c @@ -71,6 +71,22 @@ #define MRVL_TOK_VLAN_IP "vlan/ip" #define MRVL_TOK_WEIGHT "weight" +/* policer specific configuration tokens */ +#define MRVL_TOK_PLCR_ENABLE "policer_enable" +#define MRVL_TOK_PLCR_UNIT "token_unit" +#define MRVL_TOK_PLCR_UNIT_BYTES "bytes" +#define MRVL_TOK_PLCR_UNIT_PACKETS "packets" +#define MRVL_TOK_PLCR_COLOR "color_mode" +#define MRVL_TOK_PLCR_COLOR_BLIND "blind" +#define MRVL_TOK_PLCR_COLOR_AWARE "aware" +#define MRVL_TOK_PLCR_CIR "cir" +#define MRVL_TOK_PLCR_CBS "cbs" +#define MRVL_TOK_PLCR_EBS "ebs" +#define MRVL_TOK_PLCR_DEFAULT_COLOR "default_color" +#define MRVL_TOK_PLCR_DEFAULT_COLOR_GREEN "green" +#define MRVL_TOK_PLCR_DEFAULT_COLOR_YELLOW "yellow" +#define MRVL_TOK_PLCR_DEFAULT_COLOR_RED "red" + /** Number of tokens in range a-b = 2. */ #define MAX_RNG_TOKENS 2 @@ -324,6 +340,25 @@ parse_tc_cfg(struct rte_cfgfile *file, int port, int tc, } cfg->port[port].tc[tc].dscps = n; } + + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PLCR_DEFAULT_COLOR); + if (entry) { + if (!strncmp(entry, MRVL_TOK_PLCR_DEFAULT_COLOR_GREEN, + sizeof(MRVL_TOK_PLCR_DEFAULT_COLOR_GREEN))) { + cfg->port[port].tc[tc].color = PP2_PPIO_COLOR_GREEN; + } else if (!strncmp(entry, MRVL_TOK_PLCR_DEFAULT_COLOR_YELLOW, + sizeof(MRVL_TOK_PLCR_DEFAULT_COLOR_YELLOW))) { + cfg->port[port].tc[tc].color = PP2_PPIO_COLOR_YELLOW; + } else if (!strncmp(entry, MRVL_TOK_PLCR_DEFAULT_COLOR_RED, + sizeof(MRVL_TOK_PLCR_DEFAULT_COLOR_RED))) { + cfg->port[port].tc[tc].color = PP2_PPIO_COLOR_RED; + } else { + RTE_LOG(ERR, PMD, "Error while parsing: %s\n", entry); + return -1; + } + } + return 0; } @@ -396,6 +431,88 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, } entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PLCR_ENABLE); + if (entry) { + if (get_val_securely(entry, &val) < 0) + return -1; + (*cfg)->port[n].policer_enable = val; + } + + if ((*cfg)->port[n].policer_enable) { + enum pp2_cls_plcr_token_unit unit; + + /* Read policer token unit */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PLCR_UNIT); + if (entry) { + if (!strncmp(entry, MRVL_TOK_PLCR_UNIT_BYTES, + sizeof(MRVL_TOK_PLCR_UNIT_BYTES))) { + unit = PP2_CLS_PLCR_BYTES_TOKEN_UNIT; + } else if (!strncmp(entry, + MRVL_TOK_PLCR_UNIT_PACKETS, + sizeof(MRVL_TOK_PLCR_UNIT_PACKETS))) { + unit = PP2_CLS_PLCR_PACKETS_TOKEN_UNIT; + } else { + RTE_LOG(ERR, PMD, "Unknown token: %s\n", + entry); + return -1; + } + (*cfg)->port[n].policer_params.token_unit = + unit; + } + + /* Read policer color mode */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PLCR_COLOR); + if (entry) { + enum pp2_cls_plcr_color_mode mode; + + if (!strncmp(entry, MRVL_TOK_PLCR_COLOR_BLIND, + sizeof(MRVL_TOK_PLCR_COLOR_BLIND))) { + mode = PP2_CLS_PLCR_COLOR_BLIND_MODE; + } else if (!strncmp(entry, + MRVL_TOK_PLCR_COLOR_AWARE, + sizeof(MRVL_TOK_PLCR_COLOR_AWARE))) { + mode = PP2_CLS_PLCR_COLOR_AWARE_MODE; + } else { + RTE_LOG(ERR, PMD, + "Error in parsing: %s\n", + entry); + return -1; + } + (*cfg)->port[n].policer_params.color_mode = + mode; + } + + /* Read policer cir */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PLCR_CIR); + if (entry) { + if (get_val_securely(entry, &val) < 0) + return -1; + (*cfg)->port[n].policer_params.cir = val; + } + + /* Read policer cbs */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PLCR_CBS); + if (entry) { + if (get_val_securely(entry, &val) < 0) + return -1; + (*cfg)->port[n].policer_params.cbs = val; + } + + /* Read policer ebs */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PLCR_EBS); + if (entry) { + if (get_val_securely(entry, &val) < 0) + return -1; + (*cfg)->port[n].policer_params.ebs = val; + } + } + + entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_MAPPING_PRIORITY); if (entry) { if (!strncmp(entry, MRVL_TOK_VLAN_IP, @@ -450,16 +567,18 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, * @param param TC parameters entry. * @param inqs Number of MUSDK in-queues in this TC. * @param bpool Bpool for this TC. + * @param color Default color for this TC. * @returns 0 in case of success, exits otherwise. */ static int setup_tc(struct pp2_ppio_tc_params *param, uint8_t inqs, - struct pp2_bpool *bpool) + struct pp2_bpool *bpool, enum pp2_ppio_color color) { struct pp2_ppio_inq_params *inq_params; param->pkt_offset = MRVL_PKT_OFFS; param->pools[0] = bpool; + param->default_color = color; inq_params = rte_zmalloc_socket("inq_params", inqs * sizeof(*inq_params), @@ -479,6 +598,33 @@ setup_tc(struct pp2_ppio_tc_params *param, uint8_t inqs, } /** + * Setup ingress policer. + * + * @param priv Port's private data. + * @param params Pointer to the policer's configuration. + * @returns 0 in case of success, negative values otherwise. + */ +static int +setup_policer(struct mrvl_priv *priv, struct pp2_cls_plcr_params *params) +{ + char match[16]; + int ret; + + sprintf(match, "policer-%d:%d\n", priv->pp_id, priv->ppio_id); + params->match = match; + + ret = pp2_cls_plcr_init(params, &priv->policer); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to setup %s\n", match); + return -1; + } + + priv->ppio_params.inqs_params.plcr = priv->policer; + + return 0; +} + +/** * Configure RX Queues in a given port. * * Sets up RX queues, their Traffic Classes and DPDK rxq->(TC,inq) mapping. @@ -496,10 +642,13 @@ mrvl_configure_rxqs(struct mrvl_priv *priv, uint16_t portid, if (mrvl_qos_cfg == NULL || mrvl_qos_cfg->port[portid].use_global_defaults) { - /* No port configuration, use default: 1 TC, no QoS. */ + /* + * No port configuration, use default: 1 TC, no QoS, + * TC color set to green. + */ priv->ppio_params.inqs_params.num_tcs = 1; setup_tc(&priv->ppio_params.inqs_params.tcs_params[0], - max_queues, priv->bpool); + max_queues, priv->bpool, PP2_PPIO_COLOR_GREEN); /* Direct mapping of queues i.e. 0->0, 1->1 etc. */ for (i = 0; i < max_queues; ++i) { @@ -597,11 +746,14 @@ mrvl_configure_rxqs(struct mrvl_priv *priv, uint16_t portid, break; setup_tc(&priv->ppio_params.inqs_params.tcs_params[i], port_cfg->tc[i].inqs, - priv->bpool); + priv->bpool, port_cfg->tc[i].color); } priv->ppio_params.inqs_params.num_tcs = i; + if (port_cfg->policer_enable) + return setup_policer(priv, &port_cfg->policer_params); + return 0; } diff --git a/drivers/net/mrvl/mrvl_qos.h b/drivers/net/mrvl/mrvl_qos.h index ae7508c..2ff50c1 100644 --- a/drivers/net/mrvl/mrvl_qos.h +++ b/drivers/net/mrvl/mrvl_qos.h @@ -55,6 +55,7 @@ struct mrvl_qos_cfg { uint8_t inqs; uint8_t dscps; uint8_t pcps; + enum pp2_ppio_color color; } tc[MRVL_PP2_TC_MAX]; struct { uint8_t weight; @@ -64,6 +65,8 @@ struct mrvl_qos_cfg { uint16_t outqs; uint8_t default_tc; uint8_t use_global_defaults; + struct pp2_cls_plcr_params policer_params; + uint8_t policer_enable; } port[RTE_MAX_ETHPORTS]; };