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[dpdk-dev,v3,3/6] net/ixgbe: set the ITR via configuration.

Message ID 1515924222-19044-3-git-send-email-xiangxia.m.yue@gmail.com (mailing list archive)
State Not Applicable, archived
Delegated to: Helin Zhang
Headers show

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Tonghao Zhang Jan. 14, 2018, 10:03 a.m. UTC
From: Tonghao Zhang <xiangxia.m.yue@gmail.com>

With this patch, the ITR value of ixgbe PF, can be
configured as wanted.

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
---
 drivers/net/ixgbe/ixgbe_ethdev.c | 5 +----
 drivers/net/ixgbe/ixgbe_rxtx.c   | 3 ++-
 2 files changed, 3 insertions(+), 5 deletions(-)
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Patch

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 6695ce8..604ee6d 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -89,9 +89,6 @@ 
  */
 #define IXGBE_FC_LO    0x40
 
-/* Default minimum inter-interrupt interval for EITR configuration */
-#define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
-
 /* Timer value included in XOFF frames. */
 #define IXGBE_FC_PAUSE 0x680
 
@@ -5885,7 +5882,7 @@  static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
 		break;
 	}
 	IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
-			IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
+			ixgbe_calc_itr_interval(RTE_LIBRTE_IXGBE_ITR_INTERVAL));
 
 	/* set up to autoclear timer, and the vectors */
 	mask = IXGBE_EIMS_ENABLE_MASK;
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9bc8462..cb51f46 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -4695,7 +4695,8 @@  void __attribute__((cold))
 		 * at most 500us latency for a single RSC aggregation.
 		 */
 		eitr &= ~IXGBE_EITR_ITR_INT_MASK;
-		eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
+		eitr |= ixgbe_calc_itr_interval(RTE_LIBRTE_IXGBE_ITR_INTERVAL);
+		eitr |= IXGBE_EITR_CNT_WDIS;
 
 		IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
 		IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);