From patchwork Tue Dec 26 07:27:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 32689 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5E1621B35D; Tue, 26 Dec 2017 08:28:04 +0100 (CET) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 228B11B340 for ; Tue, 26 Dec 2017 08:28:02 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 1DAE9B4005A for ; Tue, 26 Dec 2017 07:28:01 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 25 Dec 2017 23:27:58 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 25 Dec 2017 23:27:58 -0800 Received: from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com [10.17.10.10]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vBQ7RvjU015574 for ; Tue, 26 Dec 2017 07:27:57 GMT Received: from uklogin.uk.solarflarecom.com (localhost.localdomain [127.0.0.1]) by uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vBQ7RuGM019696 for ; Tue, 26 Dec 2017 07:27:57 GMT From: Andrew Rybchenko To: Date: Tue, 26 Dec 2017 07:27:47 +0000 Message-ID: <1514273271-19604-3-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1514273271-19604-1-git-send-email-arybchenko@solarflare.com> References: <1514273271-19604-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-MDID: 1514273281-uYvAcImBe7+e Subject: [dpdk-dev] [PATCH 2/6] net/sfc: make Tx free threshold check datapath specific X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" EFX_TXQ_LIMIT is libefx-specifics and it should not be used for other Tx datapaths implementations (e.g. EF10 native). EF10 native Tx datapath has its own understanding of the maximum TxQ fill level imposed by EvQ clear strategy and space reserved for Tx error and flush events. Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- drivers/net/sfc/sfc_dp_tx.h | 17 +++++++++++++++++ drivers/net/sfc/sfc_ef10_tx.c | 15 +++++++++++++++ drivers/net/sfc/sfc_tx.c | 39 +++++++++++++++++++++++++++++++-------- 3 files changed, 63 insertions(+), 8 deletions(-) diff --git a/drivers/net/sfc/sfc_dp_tx.h b/drivers/net/sfc/sfc_dp_tx.h index 94d1b10..32d7681 100644 --- a/drivers/net/sfc/sfc_dp_tx.h +++ b/drivers/net/sfc/sfc_dp_tx.h @@ -78,6 +78,22 @@ struct sfc_dp_tx_qcreate_info { }; /** + * Get size of transmit and event queue rings by the number of Tx + * descriptors. + * + * @param nb_tx_desc Number of Tx descriptors + * @param txq_entries Location for number of Tx ring entries + * @param evq_entries Location for number of event ring entries + * @param txq_max_fill_level Location for maximum Tx ring fill level + * + * @return 0 or positive errno. + */ +typedef int (sfc_dp_tx_qsize_up_rings_t)(uint16_t nb_tx_desc, + unsigned int *txq_entries, + unsigned int *evq_entries, + unsigned int *txq_max_fill_level); + +/** * Allocate and initialize datapath transmit queue. * * @param port_id The port identifier @@ -144,6 +160,7 @@ struct sfc_dp_tx { #define SFC_DP_TX_FEAT_MULTI_PROCESS 0x8 #define SFC_DP_TX_FEAT_MULTI_POOL 0x10 #define SFC_DP_TX_FEAT_REFCNT 0x20 + sfc_dp_tx_qsize_up_rings_t *qsize_up_rings; sfc_dp_tx_qcreate_t *qcreate; sfc_dp_tx_qdestroy_t *qdestroy; sfc_dp_tx_qstart_t *qstart; diff --git a/drivers/net/sfc/sfc_ef10_tx.c b/drivers/net/sfc/sfc_ef10_tx.c index 0454e79..ab3334a 100644 --- a/drivers/net/sfc/sfc_ef10_tx.c +++ b/drivers/net/sfc/sfc_ef10_tx.c @@ -487,6 +487,19 @@ sfc_ef10_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } +static sfc_dp_tx_qsize_up_rings_t sfc_ef10_tx_qsize_up_rings; +static int +sfc_ef10_tx_qsize_up_rings(uint16_t nb_tx_desc, + unsigned int *txq_entries, + unsigned int *evq_entries, + unsigned int *txq_max_fill_level) +{ + *txq_entries = nb_tx_desc; + *evq_entries = nb_tx_desc; + *txq_max_fill_level = SFC_EF10_TXQ_LIMIT(*txq_entries); + return 0; +} + static sfc_dp_tx_qcreate_t sfc_ef10_tx_qcreate; static int sfc_ef10_tx_qcreate(uint16_t port_id, uint16_t queue_id, @@ -628,6 +641,7 @@ struct sfc_dp_tx sfc_ef10_tx = { SFC_DP_TX_FEAT_MULTI_POOL | SFC_DP_TX_FEAT_REFCNT | SFC_DP_TX_FEAT_MULTI_PROCESS, + .qsize_up_rings = sfc_ef10_tx_qsize_up_rings, .qcreate = sfc_ef10_tx_qcreate, .qdestroy = sfc_ef10_tx_qdestroy, .qstart = sfc_ef10_tx_qstart, @@ -644,6 +658,7 @@ struct sfc_dp_tx sfc_ef10_simple_tx = { .type = SFC_DP_TX, }, .features = SFC_DP_TX_FEAT_MULTI_PROCESS, + .qsize_up_rings = sfc_ef10_tx_qsize_up_rings, .qcreate = sfc_ef10_tx_qcreate, .qdestroy = sfc_ef10_tx_qdestroy, .qstart = sfc_ef10_tx_qstart, diff --git a/drivers/net/sfc/sfc_tx.c b/drivers/net/sfc/sfc_tx.c index d1320f4..3c9a6e9 100644 --- a/drivers/net/sfc/sfc_tx.c +++ b/drivers/net/sfc/sfc_tx.c @@ -57,7 +57,7 @@ #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000) static int -sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc, +sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level, const struct rte_eth_txconf *tx_conf) { unsigned int flags = tx_conf->txq_flags; @@ -69,10 +69,10 @@ sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc, rc = EINVAL; } - if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) { + if (tx_conf->tx_free_thresh > txq_max_fill_level) { sfc_err(sa, "TxQ free threshold too large: %u vs maximum %u", - tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc)); + tx_conf->tx_free_thresh, txq_max_fill_level); rc = EINVAL; } @@ -145,6 +145,9 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index, const struct rte_eth_txconf *tx_conf) { const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); + unsigned int txq_entries; + unsigned int evq_entries; + unsigned int txq_max_fill_level; struct sfc_txq_info *txq_info; struct sfc_evq *evq; struct sfc_txq *txq; @@ -153,18 +156,23 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index, sfc_log_init(sa, "TxQ = %u", sw_index); - rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf); + rc = sa->dp_tx->qsize_up_rings(nb_tx_desc, &txq_entries, &evq_entries, + &txq_max_fill_level); + if (rc != 0) + goto fail_size_up_rings; + + rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf); if (rc != 0) goto fail_bad_conf; SFC_ASSERT(sw_index < sa->txq_count); txq_info = &sa->txq_info[sw_index]; - SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries); - txq_info->entries = nb_tx_desc; + SFC_ASSERT(txq_entries <= sa->txq_max_entries); + txq_info->entries = txq_entries; rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index, - txq_info->entries, socket_id, &evq); + evq_entries, socket_id, &evq); if (rc != 0) goto fail_ev_qinit; @@ -193,7 +201,7 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index, info.txq_entries = txq_info->entries; info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max; info.txq_hw_ring = txq->mem.esm_base; - info.evq_entries = txq_info->entries; + info.evq_entries = evq_entries; info.evq_hw_ring = evq->mem.esm_base; info.hw_index = txq->hw_index; info.mem_bar = sa->mem_bar.esb_base; @@ -226,6 +234,7 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index, txq_info->entries = 0; fail_bad_conf: +fail_size_up_rings: sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc); return rc; } @@ -865,6 +874,19 @@ sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq) return txq; } +static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings; +static int +sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc, + unsigned int *txq_entries, + unsigned int *evq_entries, + unsigned int *txq_max_fill_level) +{ + *txq_entries = nb_tx_desc; + *evq_entries = nb_tx_desc; + *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries); + return 0; +} + static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate; static int sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id, @@ -1040,6 +1062,7 @@ struct sfc_dp_tx sfc_efx_tx = { SFC_DP_TX_FEAT_MULTI_POOL | SFC_DP_TX_FEAT_REFCNT | SFC_DP_TX_FEAT_MULTI_SEG, + .qsize_up_rings = sfc_efx_tx_qsize_up_rings, .qcreate = sfc_efx_tx_qcreate, .qdestroy = sfc_efx_tx_qdestroy, .qstart = sfc_efx_tx_qstart,