From patchwork Sun Dec 24 10:46:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 32666 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7BA951B69E; Sun, 24 Dec 2017 11:47:14 +0100 (CET) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id CEDAC1B66D for ; Sun, 24 Dec 2017 11:47:03 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 90EFCBC005A for ; Sun, 24 Dec 2017 10:47:02 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Sun, 24 Dec 2017 02:47:00 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Sun, 24 Dec 2017 02:47:00 -0800 Received: from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com [10.17.10.10]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vBOAkwRe014803 for ; Sun, 24 Dec 2017 10:46:58 GMT Received: from uklogin.uk.solarflarecom.com (localhost.localdomain [127.0.0.1]) by uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vBOAkwhP013494 for ; Sun, 24 Dec 2017 10:46:58 GMT From: Andrew Rybchenko To: Date: Sun, 24 Dec 2017 10:46:42 +0000 Message-ID: <1514112404-13398-13-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1514112404-13398-1-git-send-email-arybchenko@solarflare.com> References: <1514112404-13398-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-MDID: 1514112423-0AdKbDJ6PX30 Subject: [dpdk-dev] [PATCH 12/14] net/sfc: correct Rx checksum offloads for tunnel packets X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the case of tunnel packet, PKT_RX_{IP,L4}_CSUM_* flags correspond to inner packet checksums. There is only one flag to indicate bad external IPv4 header checksum. Signed-off-by: Andrew Rybchenko Reviewed-by: Ivan Malov --- doc/guides/nics/features/sfc_efx.ini | 2 ++ doc/guides/nics/sfc_efx.rst | 2 ++ drivers/net/sfc/sfc_ef10_rx.c | 24 ++++++++++++++++++------ 3 files changed, 22 insertions(+), 6 deletions(-) diff --git a/doc/guides/nics/features/sfc_efx.ini b/doc/guides/nics/features/sfc_efx.ini index 03890f3..6b73af9 100644 --- a/doc/guides/nics/features/sfc_efx.ini +++ b/doc/guides/nics/features/sfc_efx.ini @@ -24,6 +24,8 @@ Flow API = Y VLAN offload = P L3 checksum offload = Y L4 checksum offload = Y +Inner L3 checksum = Y +Inner L4 checksum = Y Packet type parsing = Y Rx descriptor status = Y Tx descriptor status = Y diff --git a/doc/guides/nics/sfc_efx.rst b/doc/guides/nics/sfc_efx.rst index 994e111..813cb6f 100644 --- a/doc/guides/nics/sfc_efx.rst +++ b/doc/guides/nics/sfc_efx.rst @@ -69,6 +69,8 @@ SFC EFX PMD has support for: - IPv4/IPv6 TCP/UDP receive checksum offload +- Inner IPv4/IPv6 TCP/UDP receive checksum offload + - Received packet type information - Receive side scaling (RSS) diff --git a/drivers/net/sfc/sfc_ef10_rx.c b/drivers/net/sfc/sfc_ef10_rx.c index 41c2885..e860a39 100644 --- a/drivers/net/sfc/sfc_ef10_rx.c +++ b/drivers/net/sfc/sfc_ef10_rx.c @@ -252,6 +252,10 @@ sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev, struct rte_mbuf *m) { uint32_t tun_ptype = 0; + /* Which event bit is mapped to PKT_RX_IP_CKSUM_* */ + int8_t ip_csum_err_bit; + /* Which event bit is mapped to PKT_RX_L4_CKSUM_* */ + int8_t l4_csum_err_bit; uint32_t l2_ptype = 0; uint32_t l3_ptype = 0; uint32_t l4_ptype = 0; @@ -282,6 +286,17 @@ sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev, break; } + if (tun_ptype == 0) { + ip_csum_err_bit = ESF_DZ_RX_IPCKSUM_ERR_LBN; + l4_csum_err_bit = ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN; + } else { + ip_csum_err_bit = ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN; + l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN; + if (unlikely(EFX_TEST_QWORD_BIT(rx_ev, + ESF_DZ_RX_IPCKSUM_ERR_LBN))) + ol_flags |= PKT_RX_EIP_CKSUM_BAD; + } + switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) { case ESE_DZ_ETH_TAG_CLASS_NONE: l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER : @@ -309,8 +324,7 @@ sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev, l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; ol_flags |= PKT_RX_RSS_HASH | - ((EFX_TEST_QWORD_BIT(rx_ev, - ESF_DZ_RX_IPCKSUM_ERR_LBN)) ? + ((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ? PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD); break; case ESE_DZ_L3_CLASS_IP6_FRAG: @@ -338,16 +352,14 @@ sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev, l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP : RTE_PTYPE_INNER_L4_TCP; ol_flags |= - (EFX_TEST_QWORD_BIT(rx_ev, - ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN)) ? + (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ? PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD; break; case ESE_DZ_L4_CLASS_UDP: l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP : RTE_PTYPE_INNER_L4_UDP; ol_flags |= - (EFX_TEST_QWORD_BIT(rx_ev, - ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN)) ? + (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ? PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD; break; case ESE_DZ_L4_CLASS_UNKNOWN: