From patchwork Thu Oct 26 14:05:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tonghao Zhang X-Patchwork-Id: 30979 X-Patchwork-Delegate: helin.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6A41F1B71D; Thu, 26 Oct 2017 16:05:41 +0200 (CEST) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by dpdk.org (Postfix) with ESMTP id 9E3C41B2CF for ; Thu, 26 Oct 2017 16:05:39 +0200 (CEST) Received: by mail-pf0-f193.google.com with SMTP id 17so2578430pfn.12 for ; Thu, 26 Oct 2017 07:05:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RHi/Ce/l6vJj9rXDzA7q/qyUNezOsMI0VhQPhY3NG/g=; b=glYTrLBwAZZymtxc3zfCgojXWuaA85ewKRY7DuHcC20nKaW8qYBDNJx/Alnzi2ETPd oo/NX8S6JORZSGOp3cQXTCmPVPDwqJQ4Foqg6J9vONMDF9DPsjdCr+m2zUC68WCw+nWU rkim/xBmH1Hh0ch72ZfNFCrMFfMVAOVXW7uSxOS2Z+0hegvlRuwSI9RTt0mT3Ee5Z+tg s11BuHhrrSc1WMVfFXvgLLKV1bu4y0lHh/GrMS4A1f2OAlUgHIMvgAsHvIwu/1PxQUnr GN9jJ6jMJffiiBAj2H5MD34n/oJIV99WJEKPKGsMhosYmKM+EXxXktUiAT8kr3AxXwnH pzRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RHi/Ce/l6vJj9rXDzA7q/qyUNezOsMI0VhQPhY3NG/g=; b=HtDc0I8Ehj7TAfbqa/eyR35vLJAwoi5jwiv7BVPMbph25Scd2meOrfL1ZtqAedOTyf GjguCrKLlasu8t8YW9RHbiK5vySm0yRtXaxnxUl0H3TRd2xVkcX3Z4CMno3zsMYfoBc7 q/dKgwqC8E16h05sBkeLgixvP2WJI7c2iZtMBIn3+h2XvB8+kQYVo9zEpLa2qaWPYhKy jcZS79aXRv77BpdMZUy2t2nNvE0toNYVMPUNz1467qrpG28kovhDnyUEkVGxs2Za4ZAD lL+aiKPF0JDc9Y1Gm/IfykNpmBjbrfuL0BU4eaisLsAJ/RXtir4wwBJOASEnrNznRM3e rGBg== X-Gm-Message-State: AMCzsaWwwFJcx8kQMaxJYUwZox7RnYRUwc3p4UvajKuvSKxc2qqkA+Pm fuOIxgf0Y6qf8Bmxs6h/3Zbb/w4X X-Google-Smtp-Source: ABhQp+RZIBjQ2OpIHkmVQvFcG32352PeBplk4BH/+Di/MXh3n31L7/SWc/dh3yd9zfVCRdsId5Ec2Q== X-Received: by 10.99.152.68 with SMTP id l4mr5087961pgo.443.1509026738681; Thu, 26 Oct 2017 07:05:38 -0700 (PDT) Received: from local.opencloud.tech.localdomain ([13.94.31.177]) by smtp.gmail.com with ESMTPSA id w17sm11075110pfa.70.2017.10.26.07.05.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 07:05:38 -0700 (PDT) From: xiangxia.m.yue@gmail.com To: dev@dpdk.org Cc: Tonghao Zhang Date: Thu, 26 Oct 2017 07:05:01 -0700 Message-Id: <1509026701-17478-4-git-send-email-xiangxia.m.yue@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1509026701-17478-1-git-send-email-xiangxia.m.yue@gmail.com> References: <1509026701-17478-1-git-send-email-xiangxia.m.yue@gmail.com> Subject: [dpdk-dev] [PATCH v2 4/4] net/ixgbevf: add check for rte_intr_enable. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tonghao Zhang When we bind the ixgbevf to vfio and call the rte_eth_dev_rx_intr_enable and rte_eth_dev_rx_intr_disable frequently, the interrupt setting (msi_set_mask_bit) will take more CPU as show below. rte_intr_enable call the ioctl to map the fd to interrupts frequently. perf top: 5.45% [kernel] [k] msi_set_mask_bit It is unnecessary to call the rte_intr_enable in ixgbe_dev_rx_queue_intr_enable. because the fds has been mapped to interrupt and not unmapped in ixgbe_dev_rx_queue_intr_disable. This patch add checks for using VFIO. With the patch, msi_set_mask_bit is not listed in perl any more. Any suggestion will be welcome. Signed-off-by: Tonghao Zhang --- drivers/net/ixgbe/ixgbe_ethdev.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 4cfa6ce..72f04b6 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -5631,7 +5631,9 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) RTE_SET_USED(queue_id); IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); - rte_intr_enable(intr_handle); + if (intr_handle->type == RTE_INTR_HANDLE_UIO || + intr_handle->type == RTE_INTR_HANDLE_UIO_INTX) + rte_intr_enable(intr_handle); return 0; } @@ -5680,7 +5682,10 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) mask &= (1 << (queue_id - 32)); IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); } - rte_intr_enable(intr_handle); + + if (intr_handle->type == RTE_INTR_HANDLE_UIO || + intr_handle->type == RTE_INTR_HANDLE_UIO_INTX) + rte_intr_enable(intr_handle); return 0; }