From patchwork Mon Oct 9 15:00:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 29996 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 91AF21B268; Mon, 9 Oct 2017 17:01:29 +0200 (CEST) Received: from mail-lf0-f54.google.com (mail-lf0-f54.google.com [209.85.215.54]) by dpdk.org (Postfix) with ESMTP id 1E20B1B22F for ; Mon, 9 Oct 2017 17:01:19 +0200 (CEST) Received: by mail-lf0-f54.google.com with SMTP id r129so8580634lff.8 for ; Mon, 09 Oct 2017 08:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VbKCYA6tPvmNiIDMoxbpZpeoVmtJLqXCSN4hzzDzqr4=; b=0JM3/kk8mCRPWOD1gmNxXNm5EOO8jPflxNQgMdk+WJTHdxQIWuvUjKkAl/1JSHNwx7 7pBqY1RX3NmdARL67JNJd7hcpsPf+hL01u7vOKpYukLrI8F/fJ3sV15bN5hruxxyaF2h JTFEbwkGcnkDAKq8rZyBVgYnUBGgiLRcoQdWUTOJ6TnlkiYg8/bcGMquWKr6KqTCIEN/ bR8yaUbi45zfoq+t+SBwaGj40w18Au7M0AXRFq+fHUKnr8o8skNejNkoSKLiZd76X875 bh8cVg6qxMtg5kefn9uZg+z+ooX2c1/IhgE7lRQ/ahHTMYpRP5h36Yu1J0zyaheduwGU 2CxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VbKCYA6tPvmNiIDMoxbpZpeoVmtJLqXCSN4hzzDzqr4=; b=fjdUDAGnoCD5KieiFj4Hw1UaP2rAhznqjYVdtnj3AX/f5xttqZjBWLS9XizyFWgBSg avAPLYKSafQGRtuEW0msk885p084cEctRI4NrFNRNtPXAT0Xpegkr08fdiGEKrpCEF56 dYtRzdJuBO8/9zsLtuczX2lng266kJKhFiVrKEBWQBH1lMUE8VN+QBR8IQTGY3T2e+nG na6NqsSk6K8FVU9hjSTYBUcqjgrtFaAE9mzTEdfDfIZ3239fB8lXy7nsjFBhsn7Dga3D Y/+B3haLnbvKrCrhrgZizJl4usx0x/eN/8TXUSuMnpbC83EUq8KEfsvvABimyHiwahbq 5qWw== X-Gm-Message-State: AMCzsaUgQXN/eR6hNJdKIoI1kmmGBZAqsheLbt4OVZQEe39wePivvZOc WOAAmdKprENK1JK9GvwGAdu+alAni8o= X-Google-Smtp-Source: AOwi7QCIVMYGbQvAN08k1wfV/0yK13U2kQ1Uc8WO20NT1w1ia2RHC1GRUOC0srN7AJUN7LYf6D1tCQ== X-Received: by 10.25.43.135 with SMTP id r129mr3806746lfr.130.1507561278512; Mon, 09 Oct 2017 08:01:18 -0700 (PDT) Received: from tdu.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z64sm1352637lfa.91.2017.10.09.08.01.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 08:01:17 -0700 (PDT) From: Tomasz Duszynski To: dev@dpdk.org Cc: mw@semihalf.com, dima@marvell.com, nsamsono@marvell.com, Jianbo.liu@linaro.org, Tomasz Duszynski , Jacek Siuda Date: Mon, 9 Oct 2017 17:00:39 +0200 Message-Id: <1507561244-20115-12-git-send-email-tdu@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507561244-20115-1-git-send-email-tdu@semihalf.com> References: <1507031500-11473-1-git-send-email-tdu@semihalf.com> <1507561244-20115-1-git-send-email-tdu@semihalf.com> Subject: [dpdk-dev] [PATCH v4 11/16] net/mrvl: add support for vlan filtering X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for vlan filtering. Signed-off-by: Jacek Siuda Signed-off-by: Tomasz Duszynski --- doc/guides/nics/features/mrvl.ini | 1 + drivers/net/mrvl/mrvl_ethdev.c | 39 ++++++++++++++++++++++++++++++++++++++- drivers/net/mrvl/mrvl_ethdev.h | 1 + 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/mrvl.ini b/doc/guides/nics/features/mrvl.ini index e65dea7..5d9132e 100644 --- a/doc/guides/nics/features/mrvl.ini +++ b/doc/guides/nics/features/mrvl.ini @@ -13,3 +13,4 @@ Allmulticast mode = Y Unicast MAC filter = Y Multicast MAC filter = Y RSS hash = Y +VLAN filter = Y diff --git a/drivers/net/mrvl/mrvl_ethdev.c b/drivers/net/mrvl/mrvl_ethdev.c index fe2603a..7023f5b 100644 --- a/drivers/net/mrvl/mrvl_ethdev.c +++ b/drivers/net/mrvl/mrvl_ethdev.c @@ -439,6 +439,19 @@ mrvl_dev_start(struct rte_eth_dev *dev) priv->uc_mc_flushed = 1; } + if (!priv->vlan_flushed) { + ret = pp2_ppio_flush_vlan(priv->ppio); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to flush vlan list\n"); + /* + * TODO + * once pp2_ppio_flush_vlan() is supported jump to out + * goto out; + */ + } + priv->vlan_flushed = 1; + } + /* For default QoS config, don't start classifier. */ if (mrvl_qos_cfg) { ret = mrvl_start_qos_mapping(priv); @@ -849,7 +862,8 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; - info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME; + info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME | + DEV_RX_OFFLOAD_VLAN_FILTER; info->flow_type_rss_offloads = ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP; @@ -904,6 +918,28 @@ static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, } /** + * DPDK callback to Configure a VLAN filter. + * + * @param dev + * Pointer to Ethernet device structure. + * @param vlan_id + * VLAN ID to filter. + * @param on + * Toggle filter. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +{ + struct mrvl_priv *priv = dev->data->dev_private; + + return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : + pp2_ppio_remove_vlan(priv->ppio, vlan_id); +} + +/** * Release buffers to hardware bpool (buffer-pool) * * @param rxq @@ -1211,6 +1247,7 @@ static const struct eth_dev_ops mrvl_ops = { .dev_infos_get = mrvl_dev_infos_get, .rxq_info_get = mrvl_rxq_info_get, .txq_info_get = mrvl_txq_info_get, + .vlan_filter_set = mrvl_vlan_filter_set, .rx_queue_setup = mrvl_rx_queue_setup, .rx_queue_release = mrvl_rx_queue_release, .tx_queue_setup = mrvl_tx_queue_setup, diff --git a/drivers/net/mrvl/mrvl_ethdev.h b/drivers/net/mrvl/mrvl_ethdev.h index 136c555..72af4c7 100644 --- a/drivers/net/mrvl/mrvl_ethdev.h +++ b/drivers/net/mrvl/mrvl_ethdev.h @@ -100,6 +100,7 @@ struct mrvl_priv { uint8_t bpool_bit; uint8_t rss_hf_tcp; uint8_t uc_mc_flushed; + uint8_t vlan_flushed; struct pp2_ppio_params ppio_params; struct pp2_cls_qos_tbl_params qos_tbl_params;