From patchwork Mon Oct 9 15:00:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 29995 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5CC271B261; Mon, 9 Oct 2017 17:01:28 +0200 (CEST) Received: from mail-lf0-f52.google.com (mail-lf0-f52.google.com [209.85.215.52]) by dpdk.org (Postfix) with ESMTP id E34EA1B233 for ; Mon, 9 Oct 2017 17:01:17 +0200 (CEST) Received: by mail-lf0-f52.google.com with SMTP id g70so12102381lfl.3 for ; Mon, 09 Oct 2017 08:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pHV+x1iHOoDnaoL0WukRhl31VyGcVN7FN5e4Ixfp7SM=; b=bffWXsQcwi7OUW5ZGa1CmOPzw/VUSMJoWPSdNwP3e4tBBOA6URNV/QrOV7QTrRAEk8 uE9aY8s42BYMlNi5RGDMLfGw4rXs0AtMuZRTQIU5FyVD/3FwTQdTRTxrHBNZWdV5+xn2 oqgmvpZOjvwTvQemS5oEQAox6etP16q4OtOK/6myEGxnYxSqOUKaeRDGj1tJY9Bd2Q1B tuk6Bgs+ThyvvCNMiX/nG0qIZO0T242/J1WqdE+x6nOpwVwGeM9TvovmruiMDuzvgj+m jpKwptO7dPfQRatKuE5Dfh2tYzmLqreDUNLtC622oLqJZsTceomwRtuKYy/kU+dCiIGU MHcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pHV+x1iHOoDnaoL0WukRhl31VyGcVN7FN5e4Ixfp7SM=; b=csDXXQrl0WIWOObtDrS4IXLC5V8rlCpYa7RLZ84yFXZULV2mEtimtZpQ8dYCp6BtDH u7PK3+OJNkYRMtWmO5DmgBZzZ450wdTt/sn7TrzBaxly5AOBkRnMcdgy7oNZdP61kNWG YpiQUpLK9LWtT4fILK42F99yzdsrynwYU2rhpuQFSXZVzu+wEEE5X8/TQBiiy+FlmwsJ ctEoyXrNorEsMpgcjQl9DZL79JhpIWXBKegGjgtt8L6oQkqM8+fdz3Ay45X693GWi2Ix D7UfdxehJhWHcLpie0MpxtAdyi9Qc2cHiZO2yUKyJYbmaTROKUH8iTc0Bvwswk9AC5VM VEAg== X-Gm-Message-State: AMCzsaXthlKMp5+S5etVJGbGtqsMI15w1zCpKtXVPHlbktqrr95momM2 +2FtKB5rDirb+bcEWcpaZWQHsn1jnl0= X-Google-Smtp-Source: AOwi7QCrlcuVwWBy7d2Yot+Xmxrt64NDDTyupdocL2/JYfCiogazUKpsTvVDCk56G6ftgEuxMDIVow== X-Received: by 10.25.20.29 with SMTP id k29mr3874737lfi.111.1507561277226; Mon, 09 Oct 2017 08:01:17 -0700 (PDT) Received: from tdu.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z64sm1352637lfa.91.2017.10.09.08.01.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 08:01:16 -0700 (PDT) From: Tomasz Duszynski To: dev@dpdk.org Cc: mw@semihalf.com, dima@marvell.com, nsamsono@marvell.com, Jianbo.liu@linaro.org, Tomasz Duszynski , Jacek Siuda Date: Mon, 9 Oct 2017 17:00:38 +0200 Message-Id: <1507561244-20115-11-git-send-email-tdu@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507561244-20115-1-git-send-email-tdu@semihalf.com> References: <1507031500-11473-1-git-send-email-tdu@semihalf.com> <1507561244-20115-1-git-send-email-tdu@semihalf.com> Subject: [dpdk-dev] [PATCH v4 10/16] net/mrvl: add rss hashing support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for rss hashing on rx. Signed-off-by: Jacek Siuda Signed-off-by: Tomasz Duszynski --- doc/guides/nics/features/mrvl.ini | 1 + drivers/net/mrvl/mrvl_ethdev.c | 116 +++++++++++++++++++++++++++++++++++++- drivers/net/mrvl/mrvl_ethdev.h | 1 + 3 files changed, 115 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/features/mrvl.ini b/doc/guides/nics/features/mrvl.ini index 2243749..e65dea7 100644 --- a/doc/guides/nics/features/mrvl.ini +++ b/doc/guides/nics/features/mrvl.ini @@ -12,3 +12,4 @@ Promiscuous mode = Y Allmulticast mode = Y Unicast MAC filter = Y Multicast MAC filter = Y +RSS hash = Y diff --git a/drivers/net/mrvl/mrvl_ethdev.c b/drivers/net/mrvl/mrvl_ethdev.c index daa2229..fe2603a 100644 --- a/drivers/net/mrvl/mrvl_ethdev.c +++ b/drivers/net/mrvl/mrvl_ethdev.c @@ -66,6 +66,8 @@ #define MRVL_MUSDK_HIFS_RESERVED 0x0F /* bitmask with reserved bpools */ #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 +/* bitmask with reserved kernel RSS tables */ +#define MRVL_MUSDK_RSS_RESERVED 0x01 /* maximum number of available hifs */ #define MRVL_MUSDK_HIFS_MAX 9 @@ -180,9 +182,47 @@ mrvl_reserve_bit(int *bitmap, int max) } /** + * Configure rss based on dpdk rss configuration. + * + * @param priv + * Pointer to private structure. + * @param rss_conf + * Pointer to RSS configuration. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) +{ + if (rss_conf->rss_key) + RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n"); + + if (rss_conf->rss_hf == 0) { + priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; + } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { + priv->ppio_params.inqs_params.hash_type = + PP2_PPIO_HASH_T_2_TUPLE; + } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { + priv->ppio_params.inqs_params.hash_type = + PP2_PPIO_HASH_T_5_TUPLE; + priv->rss_hf_tcp = 1; + } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { + priv->ppio_params.inqs_params.hash_type = + PP2_PPIO_HASH_T_5_TUPLE; + priv->rss_hf_tcp = 0; + } else { + return -EINVAL; + } + + return 0; +} + +/** * Ethernet device configuration. * - * Prepare the driver for a given number of TX and RX queues. + * Prepare the driver for a given number of TX and RX queues and + * configure RSS. * * @param dev * Pointer to Ethernet device structure. @@ -196,7 +236,8 @@ mrvl_dev_configure(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; - if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE) { + if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && + dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n", dev->data->dev_conf.rxmode.mq_mode); return -EINVAL; @@ -240,7 +281,16 @@ mrvl_dev_configure(struct rte_eth_dev *dev) priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; priv->nb_rx_queues = dev->data->nb_rx_queues; - return 0; + if (dev->data->nb_rx_queues == 1 && + dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { + RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n"); + priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; + + return 0; + } + + return mrvl_configure_rss(priv, + &dev->data->dev_conf.rx_adv_conf.rss_conf); } /** @@ -800,6 +850,10 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME; + info->flow_type_rss_offloads = ETH_RSS_IPV4 | + ETH_RSS_NONFRAG_IPV4_TCP | + ETH_RSS_NONFRAG_IPV4_UDP; + /* By default packets are dropped if no descriptors are available */ info->default_rxconf.rx_drop_en = 1; @@ -1085,6 +1139,59 @@ mrvl_tx_queue_release(void *txq) rte_free(q); } +/** + * Update RSS hash configuration + * + * @param dev + * Pointer to Ethernet device structure. + * @param rss_conf + * Pointer to RSS configuration. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct mrvl_priv *priv = dev->data->dev_private; + + return mrvl_configure_rss(priv, rss_conf); +} + +/** + * DPDK callback to get RSS hash configuration. + * + * @param dev + * Pointer to Ethernet device structure. + * @rss_conf + * Pointer to RSS configuration. + * + * @return + * Always 0. + */ +static int +mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct mrvl_priv *priv = dev->data->dev_private; + enum pp2_ppio_hash_type hash_type = + priv->ppio_params.inqs_params.hash_type; + + rss_conf->rss_key = NULL; + + if (hash_type == PP2_PPIO_HASH_T_NONE) + rss_conf->rss_hf = 0; + else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) + rss_conf->rss_hf = ETH_RSS_IPV4; + else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) + rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; + else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) + rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; + + return 0; +} + static const struct eth_dev_ops mrvl_ops = { .dev_configure = mrvl_dev_configure, .dev_start = mrvl_dev_start, @@ -1108,6 +1215,8 @@ static const struct eth_dev_ops mrvl_ops = { .rx_queue_release = mrvl_rx_queue_release, .tx_queue_setup = mrvl_tx_queue_setup, .tx_queue_release = mrvl_tx_queue_release, + .rss_hash_update = mrvl_rss_hash_update, + .rss_hash_conf_get = mrvl_rss_hash_conf_get, }; /** @@ -1394,6 +1503,7 @@ mrvl_init_pp2(void) memset(&init_params, 0, sizeof(init_params)); init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; + init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; return pp2_init(&init_params); } diff --git a/drivers/net/mrvl/mrvl_ethdev.h b/drivers/net/mrvl/mrvl_ethdev.h index f43f426..136c555 100644 --- a/drivers/net/mrvl/mrvl_ethdev.h +++ b/drivers/net/mrvl/mrvl_ethdev.h @@ -98,6 +98,7 @@ struct mrvl_priv { uint8_t pp_id; uint8_t ppio_id; uint8_t bpool_bit; + uint8_t rss_hf_tcp; uint8_t uc_mc_flushed; struct pp2_ppio_params ppio_params;